vc4: Expose compares at a lower level in QIR.

Before, we had some special opcodes like CMP and SNE that emitted multiple
instructions.  Now, we reduce those operations significantly, giving
optimization more to look at for reducing redundant operations.

The downside is that QOP_SF is pretty special -- we're going to have to
track it separately when we're doing instruction scheduling, and we want
to peephole it into the instruction generating the destination write in
most cases (and not allocate the destination reg, probably.  Unless it's
used for some other purpose, as well).

1 files changed, 9 insertions, 5 deletions

diff --git a/src/gallium/drivers/vc4/vc4_qir.c b/src/gallium/drivers/vc4/vc4_qir.c
index 0b0d2c11cf1..72149908422 100644
--- a/src/gallium/drivers/vc4/vc4_qir.c
+++ b/src/gallium/drivers/vc4/vc4_qir.c
@@ -43,11 +43,15 @@ static const struct qir_op_info qir_op_info[] = {
         [QOP_FMINABS] = { "fminabs", 1, 2 },
         [QOP_FMAXABS] = { "fmaxabs", 1, 2 },
 
-        [QOP_SEQ] = { "seq", 1, 2 },
-        [QOP_SNE] = { "sne", 1, 2 },
-        [QOP_SGE] = { "sge", 1, 2 },
-        [QOP_SLT] = { "slt", 1, 2 },
-        [QOP_CMP] = { "cmp", 1, 3 },
+        [QOP_SF] = { "sf", 0, 1 },
+        [QOP_SEL_X_0_NS] = { "fsel_x_0_ns", 1, 1 },
+        [QOP_SEL_X_0_NC] = { "fsel_x_0_nc", 1, 1 },
+        [QOP_SEL_X_0_ZS] = { "fsel_x_0_zs", 1, 1 },
+        [QOP_SEL_X_0_ZC] = { "fsel_x_0_zc", 1, 1 },
+        [QOP_SEL_X_Y_NS] = { "fsel_x_y_ns", 1, 2 },
+        [QOP_SEL_X_Y_NC] = { "fsel_x_y_nc", 1, 2 },
+        [QOP_SEL_X_Y_ZS] = { "fsel_x_y_zs", 1, 2 },
+        [QOP_SEL_X_Y_ZC] = { "fsel_x_y_zc", 1, 2 },
 
         [QOP_FTOI] = { "ftoi", 1, 1 },
         [QOP_ITOF] = { "itof", 1, 1 },