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authorEric Anholt <[email protected]>2016-07-26 17:31:44 -0700
committerEric Anholt <[email protected]>2016-08-22 11:52:26 -0700
commite8378fee0c20ecd26451c079c725420077606cb9 (patch)
tree3603185648555d9e8a7a70efa52a79f2f97fd629 /src/gallium/drivers/vc4/vc4_program.c
parent475ce61d1aa0fb06202511b4ea8ad9bd1fab64d0 (diff)
nir: Define system values for vc4's blending-lowering arguments.
In the GLSL-to-NIR conversion of VC4, I had a bit of trouble with what I was calling the "state uniforms" that I was putting into the NIR fighting with its other lowering passes. Instead of using magic uniform base numbers in the backend, follow the lead of load_user_clip_plane and just define system values for them. v2: Fix unintended change to channel_num, drop unspecified const_index value on blend_const_color_r_float. Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/gallium/drivers/vc4/vc4_program.c')
-rw-r--r--src/gallium/drivers/vc4/vc4_program.c56
1 files changed, 31 insertions, 25 deletions
diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index 5acb7a75919..24206980369 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -110,21 +110,6 @@ indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
return qir_TEX_RESULT(c);
}
-nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
- enum quniform_contents contents)
-{
- nir_intrinsic_instr *intr =
- nir_intrinsic_instr_create(b->shader,
- nir_intrinsic_load_uniform);
- nir_intrinsic_set_base(intr,
- (VC4_NIR_STATE_UNIFORM_OFFSET + contents) * 4);
- intr->num_components = 1;
- intr->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
- nir_ssa_dest_init(&intr->instr, &intr->dest, 1, 32, NULL);
- nir_builder_instr_insert(b, &intr->instr);
- return &intr->dest.ssa;
-}
-
nir_ssa_def *
vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
{
@@ -1567,16 +1552,9 @@ ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
assert(offset % 4 == 0);
/* We need dwords */
offset = offset / 4;
- if (offset < VC4_NIR_STATE_UNIFORM_OFFSET) {
- ntq_store_dest(c, &instr->dest, 0,
- qir_uniform(c, QUNIFORM_UNIFORM,
- offset));
- } else {
- ntq_store_dest(c, &instr->dest, 0,
- qir_uniform(c, offset -
- VC4_NIR_STATE_UNIFORM_OFFSET,
- 0));
- }
+ ntq_store_dest(c, &instr->dest, 0,
+ qir_uniform(c, QUNIFORM_UNIFORM,
+ offset));
} else {
ntq_store_dest(c, &instr->dest, 0,
indirect_uniform_load(c, instr));
@@ -1592,6 +1570,34 @@ ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
}
break;
+ case nir_intrinsic_load_blend_const_color_r_float:
+ case nir_intrinsic_load_blend_const_color_g_float:
+ case nir_intrinsic_load_blend_const_color_b_float:
+ case nir_intrinsic_load_blend_const_color_a_float:
+ ntq_store_dest(c, &instr->dest, 0,
+ qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
+ (instr->intrinsic -
+ nir_intrinsic_load_blend_const_color_r_float),
+ 0));
+ break;
+
+ case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
+ ntq_store_dest(c, &instr->dest, 0,
+ qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
+ 0));
+ break;
+
+ case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
+ ntq_store_dest(c, &instr->dest, 0,
+ qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
+ 0));
+ break;
+
+ case nir_intrinsic_load_alpha_ref_float:
+ ntq_store_dest(c, &instr->dest, 0,
+ qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
+ break;
+
case nir_intrinsic_load_sample_mask_in:
ntq_store_dest(c, &instr->dest, 0,
qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));