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authorEric Anholt <[email protected]>2016-08-04 17:31:02 -0700
committerEric Anholt <[email protected]>2016-08-19 13:11:36 -0700
commit5adee83806f764d60c629027dc0ee38cef3cb87a (patch)
treefbdee78f4e7c54c1f2be5adde17ac88fddfb0c26 /src/gallium/drivers/vc4/vc4_nir_lower_io.c
parentf8fecc396abf00bb6e3e31087875c834981fa699 (diff)
vc4: Switch store_output to using nir_lower_io_to_scalar / component.
Diffstat (limited to 'src/gallium/drivers/vc4/vc4_nir_lower_io.c')
-rw-r--r--src/gallium/drivers/vc4/vc4_nir_lower_io.c42
1 files changed, 3 insertions, 39 deletions
diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_io.c b/src/gallium/drivers/vc4/vc4_nir_lower_io.c
index ad96ef5ad82..3d08b648125 100644
--- a/src/gallium/drivers/vc4/vc4_nir_lower_io.c
+++ b/src/gallium/drivers/vc4/vc4_nir_lower_io.c
@@ -29,9 +29,9 @@
* Walks the NIR generated by TGSI-to-NIR to lower its io intrinsics into
* something amenable to the VC4 architecture.
*
- * Currently, it splits outputs, VS inputs, and uniforms into scalars, drops
- * any non-position outputs in coordinate shaders, and fixes up the addressing
- * on indirect uniform loads. FS input scalarization is handled by
+ * Currently, it splits VS inputs and uniforms into scalars, drops any
+ * non-position outputs in coordinate shaders, and fixes up the addressing on
+ * indirect uniform loads. FS input and VS output scalarization is handled by
* nir_lower_io_to_scalar().
*/
@@ -319,42 +319,6 @@ vc4_nir_lower_output(struct vc4_compile *c, nir_builder *b,
nir_instr_remove(&intr->instr);
return;
}
-
- /* Color output is lowered by vc4_nir_lower_blend(). */
- if (c->stage == QSTAGE_FRAG &&
- (output_var->data.location == FRAG_RESULT_COLOR ||
- output_var->data.location == FRAG_RESULT_DATA0 ||
- output_var->data.location == FRAG_RESULT_SAMPLE_MASK)) {
- nir_intrinsic_set_base(intr, nir_intrinsic_base(intr) * 4);
- return;
- }
-
- /* All TGSI-to-NIR outputs are VEC4. */
- assert(intr->num_components == 4);
-
- /* We only accept direct outputs and TGSI only ever gives them to us
- * with an offset value of 0.
- */
- assert(nir_src_as_const_value(intr->src[1]) &&
- nir_src_as_const_value(intr->src[1])->u32[0] == 0);
-
- b->cursor = nir_before_instr(&intr->instr);
-
- for (unsigned i = 0; i < intr->num_components; i++) {
- nir_intrinsic_instr *intr_comp =
- nir_intrinsic_instr_create(c->s, nir_intrinsic_store_output);
- intr_comp->num_components = 1;
- nir_intrinsic_set_base(intr_comp,
- nir_intrinsic_base(intr) * 4 + i);
-
- assert(intr->src[0].is_ssa);
- intr_comp->src[0] =
- nir_src_for_ssa(nir_channel(b, intr->src[0].ssa, i));
- intr_comp->src[1] = nir_src_for_ssa(nir_imm_int(b, 0));
- nir_builder_instr_insert(b, &intr_comp->instr);
- }
-
- nir_instr_remove(&intr->instr);
}
static void