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authorMarek Olšák <[email protected]>2018-06-21 22:50:51 -0400
committerMarek Olšák <[email protected]>2018-06-25 18:33:58 -0400
commit3da693b7d98782437c25b1f6c2d0efb3a398246b (patch)
tree34ee4de05b7c3693d646e4651b941beb982d4853 /src/gallium/drivers/radeonsi
parent2d64a68c6f38b6dab8f0d2b8968e009c25bcc9f5 (diff)
ac/surface: move cmask_size/alignment into radeon_surf
cmask_size is changed to uint32_t because it can't be greater than 4GB. Reviewed-by: Timothy Arceri <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
-rw-r--r--src/gallium/drivers/radeonsi/si_texture.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index cb6cf196148..4ae02669443 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1050,11 +1050,11 @@ void si_print_texture_info(struct si_screen *sscreen,
}
if (tex->cmask.size) {
- u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", "
+ u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, "
"alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
tex->cmask.offset,
- tex->surface.u.gfx9.cmask_size,
- tex->surface.u.gfx9.cmask_alignment,
+ tex->surface.cmask_size,
+ tex->surface.cmask_alignment,
tex->surface.u.gfx9.cmask.rb_aligned,
tex->surface.u.gfx9.cmask.pipe_aligned);
}