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authorMarek Olšák <[email protected]>2018-06-05 02:09:52 -0400
committerMarek Olšák <[email protected]>2018-06-19 12:52:28 -0400
commit0d685ba2900734d8af4a47ef9586d511ad754ce4 (patch)
tree67380169c1c74ac926a6e445fd58479dd53e6af8 /src/gallium/drivers/radeonsi
parente93fe403bc0e85994d1be59ad3ad5bf65ecbf971 (diff)
radeonsi: make sure LS-HS vector lanes are reasonably occupied
Tested-by: Dieter Nützel <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index e7f8389caf3..d61374e95ca 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -170,6 +170,14 @@ static bool si_emit_derived_tess_state(struct si_context *sctx,
*/
*num_patches = MIN2(*num_patches, 40);
+ /* Make sure that vector lanes are reasonably occupied. It probably
+ * doesn't matter much because this is LS-HS, and TES is likely to
+ * occupy significantly more CUs.
+ */
+ unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
+ if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
+ *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
+
if (sctx->chip_class == SI) {
/* SI bug workaround, related to power management. Limit LS-HS
* threadgroups to only one wave.