diff options
| author | Marek Olšák <[email protected]> | 2016-06-06 02:01:36 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-06-08 00:22:45 +0200 |
| commit | 7c6e88b6430b3a805f982c7f8b34d1f79a8fc09c (patch) | |
| tree | 28a39768ae291cf977bda60943201ce2f55113e3 /src/gallium/drivers/radeonsi/si_state.c | |
| parent | 9a472a3e0b20923e9a42d362c6fad546c591f3d1 (diff) | |
radeonsi: allow MSAA resolving into a texture that has DCC enabled
Since DCC is enabled almost everywhere now, it's important not to disable
this fast path.
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 270b9fda079..92448a47fab 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2443,8 +2443,16 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom } cb_color_info = cb->cb_color_info | tex->cb_color_info; - if (tex->dcc_offset && cb->level_info->dcc_enabled) - cb_color_info |= S_028C70_DCC_ENABLE(1); + + if (tex->dcc_offset && cb->level_info->dcc_enabled) { + bool is_msaa_resolve_dst = state->cbufs[0] && + state->cbufs[0]->texture->nr_samples > 1 && + state->cbufs[1] == &cb->base && + state->cbufs[1]->texture->nr_samples <= 1; + + if (!is_msaa_resolve_dst) + cb_color_info |= S_028C70_DCC_ENABLE(1); + } radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, sctx->b.chip_class >= VI ? 14 : 13); |