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authorNicolai Hähnle <[email protected]>2016-06-17 20:08:42 +0200
committerNicolai Hähnle <[email protected]>2016-06-20 18:29:55 +0200
commit1167905c41d4594153d6649c0cade96a83831cbd (patch)
treefcbda64dd20a5c06a7875328f4e9dae2057eeb21 /src/gallium/drivers/radeonsi/si_state.c
parent650137a9c8fb5ae4a214440ca3ebc43461e2d394 (diff)
radeonsi: use trapezoid distribution for tess on Fiji and Polaris
This yields a small performance improvement in Unigine Heaven. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c22
1 files changed, 17 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 6be2f4be1f6..1cef1dc8750 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3839,16 +3839,28 @@ static void si_init_config(struct si_context *sctx)
}
if (sctx->b.chip_class >= VI) {
+ unsigned vgt_tess_distribution;
+
si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
S_028424_OVERWRITE_COMBINER_WATERMARK(4));
si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
- si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
- S_028B50_ACCUM_ISOLINE(32) |
- S_028B50_ACCUM_TRI(11) |
- S_028B50_ACCUM_QUAD(11) |
- S_028B50_DONUT_SPLIT(16));
+
+ vgt_tess_distribution =
+ S_028B50_ACCUM_ISOLINE(32) |
+ S_028B50_ACCUM_TRI(11) |
+ S_028B50_ACCUM_QUAD(11) |
+ S_028B50_DONUT_SPLIT(16);
+
+ /* Testing with Unigine Heaven extreme tesselation yielded best results
+ * with TRAP_SPLIT = 3.
+ */
+ if (sctx->b.family == CHIP_FIJI ||
+ sctx->b.family >= CHIP_POLARIS10)
+ vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
+
+ si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
}
if (sctx->b.family == CHIP_STONEY)