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authorMarek Olšák <[email protected]>2017-04-22 19:34:26 +0200
committerMarek Olšák <[email protected]>2017-04-28 21:47:35 +0200
commit4e5006202810ae3450a28372a2bf79663e1b6066 (patch)
tree31bcff81fb19d1f70cc3d0734f138ee7046313d0 /src/gallium/drivers/radeonsi/si_pm4.h
parent2823e15f60c571ee415788ebc20f1bf00206f2a5 (diff)
radeonsi: pass tessellation ring addresses via user SGPRs
This removes s_load_dword latency for tess rings. We need just 1 SGPR for the address if we use 64K alignment. The final asm for recreating the descriptor is: // s2 is (address >> 16) s_mov_b32 s3, 0 s_lshl_b64 s[4:5], s[2:3], 16 s_mov_b32 s6, -1 s_mov_b32 s7, 0x27fac v2: bitcast the descriptor type from v2i64 to v4i32 Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_pm4.h')
-rw-r--r--src/gallium/drivers/radeonsi/si_pm4.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h
index 106abe1ec7d..189c4819a55 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_pm4.h
@@ -30,7 +30,7 @@
#include "radeon/radeon_winsys.h"
#define SI_PM4_MAX_DW 176
-#define SI_PM4_MAX_BO 1
+#define SI_PM4_MAX_BO 3
// forward defines
struct si_context;