From 4e5006202810ae3450a28372a2bf79663e1b6066 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sat, 22 Apr 2017 19:34:26 +0200 Subject: radeonsi: pass tessellation ring addresses via user SGPRs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This removes s_load_dword latency for tess rings. We need just 1 SGPR for the address if we use 64K alignment. The final asm for recreating the descriptor is: // s2 is (address >> 16) s_mov_b32 s3, 0 s_lshl_b64 s[4:5], s[2:3], 16 s_mov_b32 s6, -1 s_mov_b32 s7, 0x27fac v2: bitcast the descriptor type from v2i64 to v4i32 Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_pm4.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gallium/drivers/radeonsi/si_pm4.h') diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h index 106abe1ec7d..189c4819a55 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.h +++ b/src/gallium/drivers/radeonsi/si_pm4.h @@ -30,7 +30,7 @@ #include "radeon/radeon_winsys.h" #define SI_PM4_MAX_DW 176 -#define SI_PM4_MAX_BO 1 +#define SI_PM4_MAX_BO 3 // forward defines struct si_context; -- cgit v1.2.3