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author | Marek Olšák <[email protected]> | 2018-10-17 12:26:54 -0400 |
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committer | Marek Olšák <[email protected]> | 2018-10-18 16:08:56 -0400 |
commit | 77bcbe712e5224043101bdfc19aee7038bc8b0ee (patch) | |
tree | e6817f8e66a8e679e93bdd604638ca64557536af /src/gallium/drivers/radeonsi/si_pipe.h | |
parent | eae8f49fc65e6e625f5e05d38c3bf1b61b84bd3d (diff) |
radeonsi: clamp point size to the limit
This fixes dEQP-GLES2.functional.rasterization.limits.points.
Broken by: ea039f789d9b54e1bd1d644b6a29863ca3500314
Tested-by: Jakob Bornecrantz <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_pipe.h')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 6edc06cece7..dc95afb7421 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -48,6 +48,7 @@ #define SI_BASE_VERTEX_UNKNOWN INT_MIN #define SI_RESTART_INDEX_UNKNOWN INT_MIN #define SI_NUM_SMOOTH_AA_SAMPLES 8 +#define SI_MAX_POINT_SIZE 2048 #define SI_GS_PER_ES 128 /* Alignment for optimal CP DMA performance. */ #define SI_CPDMA_ALIGNMENT 32 |