radeonsi: re-order the SQ_xx performance counter blocks

This is yet another change motivated by appeasing AMD GPUPerfStudio's
hardcoding of performance counter group numbers.

Reviewed-by: Edward O'Callaghan <[email protected]>
Acked-by: Marek Olšák <[email protected]>

1 files changed, 21 insertions, 0 deletions

diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c
index b6588667dc3..f944a52b8dc 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -79,6 +79,23 @@ struct si_pc_block {
 	unsigned instances;
 };
 
+/* The order is chosen to be compatible with GPUPerfStudio's hardcoding of
+ * performance counter group IDs.
+ */
+static const char * const si_pc_shader_type_suffixes[] = {
+	"", "_ES", "_GS", "_VS", "_PS", "_LS", "_HS", "_CS"
+};
+
+static const unsigned si_pc_shader_type_bits[] = {
+	0x7f,
+	S_036780_ES_EN(1),
+	S_036780_GS_EN(1),
+	S_036780_VS_EN(1),
+	S_036780_PS_EN(1),
+	S_036780_LS_EN(1),
+	S_036780_HS_EN(1),
+	S_036780_CS_EN(1),
+};
 
 static struct si_pc_block_base cik_CB = {
 	.name = "CB",
@@ -662,6 +679,10 @@ void si_init_perfcounters(struct si_screen *screen)
 		pc->num_stop_cs_dwords += 6;
 	}
 
+	pc->num_shader_types = ARRAY_SIZE(si_pc_shader_type_bits);
+	pc->shader_type_suffixes = si_pc_shader_type_suffixes;
+	pc->shader_type_bits = si_pc_shader_type_bits;
+
 	pc->get_size = si_pc_get_size;
 	pc->emit_instance = si_pc_emit_instance;
 	pc->emit_shaders = si_pc_emit_shaders;