diff options
| author | Marek Olšák <[email protected]> | 2019-06-18 19:06:57 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-06-24 21:04:10 -0400 |
| commit | 1d6e358c36d37c043ff28a93262f45033adadb1a (patch) | |
| tree | 78be5afe738b9fd6f76e5ce79cbe2b6bf31d72e3 /src/gallium/drivers/radeonsi/si_gfx_cs.c | |
| parent | aa8d6e05074449719f218618f2cf7dd1b5ed8968 (diff) | |
radeonsi: rename and re-document cache flush flags
SMEM and VMEM caches are L0 on gfx10.
Tested-by: Dieter Nützel <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_gfx_cs.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_gfx_cs.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index de0909904c8..9386df3a615 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -83,7 +83,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, if (!ctx->screen->info.kernel_flushes_tc_l2_after_ib) { wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH | - SI_CONTEXT_INV_GLOBAL_L2; + SI_CONTEXT_INV_L2; } else if (ctx->chip_class == GFX6) { /* The kernel flushes L2 before shaders are finished. */ wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | @@ -304,9 +304,9 @@ void si_begin_new_gfx_cs(struct si_context *ctx) * TODO: Do we also need to invalidate CB & DB caches? */ ctx->flags |= SI_CONTEXT_INV_ICACHE | - SI_CONTEXT_INV_SMEM_L1 | - SI_CONTEXT_INV_VMEM_L1 | - SI_CONTEXT_INV_GLOBAL_L2 | + SI_CONTEXT_INV_SCACHE | + SI_CONTEXT_INV_VCACHE | + SI_CONTEXT_INV_L2 | SI_CONTEXT_START_PIPELINE_STATS; ctx->cs_shader_state.initialized = false; |