diff options
| author | Marek Olšák <[email protected]> | 2019-06-18 19:06:57 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-06-24 21:04:10 -0400 |
| commit | 1d6e358c36d37c043ff28a93262f45033adadb1a (patch) | |
| tree | 78be5afe738b9fd6f76e5ce79cbe2b6bf31d72e3 /src/gallium/drivers/radeonsi/si_compute.c | |
| parent | aa8d6e05074449719f218618f2cf7dd1b5ed8968 (diff) | |
radeonsi: rename and re-document cache flush flags
SMEM and VMEM caches are L0 on gfx10.
Tested-by: Dieter Nützel <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_compute.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_compute.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 7e5259b70a0..63c95ed2604 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -917,7 +917,7 @@ static void si_launch_grid( /* Indirect buffers use TC L2 on GFX9, but not older hw. */ if (sctx->chip_class <= GFX8 && si_resource(info->indirect)->TC_L2_dirty) { - sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; + sctx->flags |= SI_CONTEXT_WB_L2; si_resource(info->indirect)->TC_L2_dirty = false; } } |