radeonsi: simplify logic around vi_separate_dcc_try_enable

1 files changed, 10 insertions, 13 deletions

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 5cbbc89b60e..6313f904b41 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -435,19 +435,16 @@ static void si_do_fast_color_clear(struct si_context *sctx,
 		/* Fast clear is the most appropriate place to enable DCC for
 		 * displayable surfaces.
 		 */
-		if (sctx->chip_class >= VI &&
-		    !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
-			vi_separate_dcc_try_enable(sctx, tex);
-
-			/* RB+ isn't supported with a CMASK clear only on Stoney,
-			 * so all clears are considered to be hypothetically slow
-			 * clears, which is weighed when determining whether to
-			 * enable separate DCC.
-			 */
-			if (tex->dcc_gather_statistics &&
-			    sctx->family == CHIP_STONEY)
-				tex->num_slow_clears++;
-		}
+		vi_separate_dcc_try_enable(sctx, tex);
+
+		/* RB+ isn't supported with a CMASK clear only on Stoney,
+		 * so all clears are considered to be hypothetically slow
+		 * clears, which is weighed when determining whether to
+		 * enable separate DCC.
+		 */
+		if (tex->dcc_gather_statistics &&
+		    sctx->family == CHIP_STONEY)
+			tex->num_slow_clears++;
 
 		bool need_decompress_pass = false;