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authorVincent Lejeune <[email protected]>2012-10-08 15:37:39 +0200
committerVincent Lejeune <[email protected]>2012-10-10 22:03:33 +0200
commit5090ce42e4437a2f9d1043309417b3fa930ee330 (patch)
tree1d94b03c820907598f23cae4af28ed47ec6cedd8 /src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
parent9a6bb3f645eec8ce9b04584f1bd8e76095f20a06 (diff)
radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round.posinf
Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c')
-rw-r--r--src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 3b251938774..57ec372d097 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1117,8 +1117,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
- bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem;
- bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.AMDIL.round.posinf.";
+ bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
+ bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";