diff options
| author | Vincent Lejeune <[email protected]> | 2012-10-03 22:28:59 +0200 |
|---|---|---|
| committer | Vincent Lejeune <[email protected]> | 2012-10-10 22:02:28 +0200 |
| commit | 23e11ac8354b3807d9c69c19bcf958cca23ffc04 (patch) | |
| tree | 60358080036563ada5f2fb989b47d984b739c973 /src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | |
| parent | 876b42663c4a72040a2084ed094d5a496b86aecd (diff) | |
radeon/llvm: add support for cos/sin intrinsic
Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c')
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c index 3c291220884..8b5eaed5e26 100644 --- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c +++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c @@ -1133,8 +1133,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx) bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp."; bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem; bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt"; - bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.AMDGPU.cos"; + bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_readonly; + bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32"; bld_base->op_actions[TGSI_OPCODE_DIV].emit = build_tgsi_intrinsic_nomem; bld_base->op_actions[TGSI_OPCODE_DIV].intr_name = "llvm.AMDGPU.div"; bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit; @@ -1175,8 +1175,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx) bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp; bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp; bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp; - bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.AMDGPU.sin"; + bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_readonly; + bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32"; bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args; bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex"; bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args; |