radeonsi: re-order the SQ_xx performance counter blocks

This is yet another change motivated by appeasing AMD GPUPerfStudio's
hardcoding of performance counter group numbers.

Reviewed-by: Edward O'Callaghan <[email protected]>
Acked-by: Marek Olšák <[email protected]>

1 files changed, 4 insertions, 18 deletions

diff --git a/src/gallium/drivers/radeon/r600_query.h b/src/gallium/drivers/radeon/r600_query.h
index dbc950fed43..8b2c4e3fe93 100644
--- a/src/gallium/drivers/radeon/r600_query.h
+++ b/src/gallium/drivers/radeon/r600_query.h
@@ -166,24 +166,6 @@ enum {
 	R600_PC_BLOCK_SHADER_WINDOWED = (1 << 4),
 };
 
-/* Shader enable bits. Chosen to coincide with SQ_PERFCOUNTER_CTRL values */
-enum {
-	R600_PC_SHADER_PS = (1 << 0),
-	R600_PC_SHADER_VS = (1 << 1),
-	R600_PC_SHADER_GS = (1 << 2),
-	R600_PC_SHADER_ES = (1 << 3),
-	R600_PC_SHADER_HS = (1 << 4),
-	R600_PC_SHADER_LS = (1 << 5),
-	R600_PC_SHADER_CS = (1 << 6),
-
-	R600_PC_SHADER_ALL = R600_PC_SHADER_PS | R600_PC_SHADER_VS |
-			     R600_PC_SHADER_GS | R600_PC_SHADER_ES |
-			     R600_PC_SHADER_HS | R600_PC_SHADER_LS |
-			     R600_PC_SHADER_CS,
-
-	R600_PC_SHADER_WINDOWING = (1 << 31),
-};
-
 /* Describes a hardware block with performance counters. Multiple instances of
  * each block, possibly per-SE, may exist on the chip. Depending on the block
  * and on the user's configuration, we either
@@ -220,6 +202,10 @@ struct r600_perfcounters {
 	unsigned num_instance_cs_dwords;
 	unsigned num_shaders_cs_dwords;
 
+	unsigned num_shader_types;
+	const char * const *shader_type_suffixes;
+	const unsigned *shader_type_bits;
+
 	void (*get_size)(struct r600_perfcounter_block *,
 			 unsigned count, unsigned *selectors,
 			 unsigned *num_select_dw, unsigned *num_read_dw);