diff options
| author | Tom Stellard <[email protected]> | 2012-09-13 15:20:46 +0000 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-09-21 19:30:58 +0000 |
| commit | 3882d7b5e434fb1e0e024b1cee2a885b3ad251bf (patch) | |
| tree | 718f6a44ca833cf82d65d2efc3beca15f83c68e5 /src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp | |
| parent | e866dbd1b538ce086ef0a8b7e5ae7ae8e81a72e7 (diff) | |
radeon/llvm: Add support for v4f32 stores on R600
Diffstat (limited to 'src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp index 65fd22f8cf5..8ad8213eaf6 100644 --- a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp @@ -158,7 +158,8 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, return; } else { switch(MI.getOpcode()) { - case AMDGPU::RAT_WRITE_CACHELESS_eg: + case AMDGPU::RAT_WRITE_CACHELESS_32_eg: + case AMDGPU::RAT_WRITE_CACHELESS_128_eg: { uint64_t inst = getBinaryCodeForInstr(MI, Fixups); EmitByte(INSTR_NATIVE, OS); |