From 3882d7b5e434fb1e0e024b1cee2a885b3ad251bf Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 13 Sep 2012 15:20:46 +0000 Subject: radeon/llvm: Add support for v4f32 stores on R600 --- src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp') diff --git a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp index 65fd22f8cf5..8ad8213eaf6 100644 --- a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp @@ -158,7 +158,8 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, return; } else { switch(MI.getOpcode()) { - case AMDGPU::RAT_WRITE_CACHELESS_eg: + case AMDGPU::RAT_WRITE_CACHELESS_32_eg: + case AMDGPU::RAT_WRITE_CACHELESS_128_eg: { uint64_t inst = getBinaryCodeForInstr(MI, Fixups); EmitByte(INSTR_NATIVE, OS); -- cgit v1.2.3