radeon/llvm: Remove IL_cmp DAG node

1 files changed, 2 insertions, 340 deletions

diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp
index c9fd4a1902b..f5f756199d9 100644
--- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp
@@ -85,333 +85,6 @@ getConversionNode(SelectionDAG &DAG, SDValue& Src, SDValue& Dst, bool asType)
   }
   return Src;
 }
-// CondCCodeToCC - Convert a DAG condition code to a AMDIL CC
-// condition.
-  static AMDILCC::CondCodes
-CondCCodeToCC(ISD::CondCode CC, const MVT::SimpleValueType& type)
-{
-  switch (CC) {
-    default:
-      {
-        errs()<<"Condition Code: "<< (unsigned int)CC<<"\n";
-        assert(0 && "Unknown condition code!");
-      }
-    case ISD::SETO:
-      switch(type) {
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_O;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_O;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETUO:
-      switch(type) {
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_UO;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_UO;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETGT:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_I_GT;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_GT;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_GT;
-        case MVT::i64:
-          return AMDILCC::IL_CC_L_GT;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETGE:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_I_GE;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_GE;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_GE;
-        case MVT::i64:
-          return AMDILCC::IL_CC_L_GE;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETLT:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_I_LT;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_LT;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_LT;
-        case MVT::i64:
-          return AMDILCC::IL_CC_L_LT;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETLE:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_I_LE;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_LE;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_LE;
-        case MVT::i64:
-          return AMDILCC::IL_CC_L_LE;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETNE:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_I_NE;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_NE;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_NE;
-        case MVT::i64:
-          return AMDILCC::IL_CC_L_NE;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETEQ:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_I_EQ;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_EQ;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_EQ;
-        case MVT::i64:
-          return AMDILCC::IL_CC_L_EQ;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETUGT:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_U_GT;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_UGT;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_UGT;
-        case MVT::i64:
-          return AMDILCC::IL_CC_UL_GT;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETUGE:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_U_GE;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_UGE;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_UGE;
-        case MVT::i64:
-          return AMDILCC::IL_CC_UL_GE;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETULT:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_U_LT;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_ULT;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_ULT;
-        case MVT::i64:
-          return AMDILCC::IL_CC_UL_LT;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETULE:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_U_LE;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_ULE;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_ULE;
-        case MVT::i64:
-          return AMDILCC::IL_CC_UL_LE;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETUNE:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_U_NE;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_UNE;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_UNE;
-        case MVT::i64:
-          return AMDILCC::IL_CC_UL_NE;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETUEQ:
-      switch (type) {
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-          return AMDILCC::IL_CC_U_EQ;
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_UEQ;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_UEQ;
-        case MVT::i64:
-          return AMDILCC::IL_CC_UL_EQ;
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETOGT:
-      switch (type) {
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_OGT;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_OGT;
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-        case MVT::i64:
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETOGE:
-      switch (type) {
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_OGE;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_OGE;
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-        case MVT::i64:
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETOLT:
-      switch (type) {
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_OLT;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_OLT;
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-        case MVT::i64:
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETOLE:
-      switch (type) {
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_OLE;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_OLE;
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-        case MVT::i64:
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETONE:
-      switch (type) {
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_ONE;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_ONE;
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-        case MVT::i64:
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-    case ISD::SETOEQ:
-      switch (type) {
-        case MVT::f32:
-          return AMDILCC::IL_CC_F_OEQ;
-        case MVT::f64:
-          return AMDILCC::IL_CC_D_OEQ;
-        case MVT::i1:
-        case MVT::i8:
-        case MVT::i16:
-        case MVT::i32:
-        case MVT::i64:
-        default:
-          assert(0 && "Opcode combination not generated correctly!");
-          return AMDILCC::COND_ERROR;
-      };
-  };
-}
 
 //===----------------------------------------------------------------------===//
 // TargetLowering Implementation Help Functions End
@@ -632,13 +305,6 @@ AMDILTargetLowering::getTargetNodeName(unsigned Opcode) const
     case AMDILISD::UMUL: return "AMDILISD::UMUL";
     case AMDILISD::DIV_INF: return "AMDILISD::DIV_INF";
     case AMDILISD::VBUILD: return "AMDILISD::VBUILD";
-    case AMDILISD::CMP: return "AMDILISD::CMP";
-    case AMDILISD::IL_CC_I_LT: return "AMDILISD::IL_CC_I_LT";
-    case AMDILISD::IL_CC_I_LE: return "AMDILISD::IL_CC_I_LE";
-    case AMDILISD::IL_CC_I_GT: return "AMDILISD::IL_CC_I_GT";
-    case AMDILISD::IL_CC_I_GE: return "AMDILISD::IL_CC_I_GE";
-    case AMDILISD::IL_CC_I_EQ: return "AMDILISD::IL_CC_I_EQ";
-    case AMDILISD::IL_CC_I_NE: return "AMDILISD::IL_CC_I_NE";
     case AMDILISD::RET_FLAG: return "AMDILISD::RET_FLAG";
     case AMDILISD::BRANCH_COND: return "AMDILISD::BRANCH_COND";
 
@@ -1162,14 +828,10 @@ AMDILTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const
   SDValue r1 = RHS;
 
   // ilt r10, r0, 0
-  SDValue r10 = DAG.getNode(AMDILISD::CMP, DL, OVT,
-      DAG.getConstant(CondCCodeToCC(ISD::SETLT, MVT::i32), MVT::i32),
-      r0, DAG.getConstant(0, OVT));
+  SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);
 
   // ilt r11, r1, 0
-  SDValue r11 = DAG.getNode(AMDILISD::CMP, DL, OVT, 
-      DAG.getConstant(CondCCodeToCC(ISD::SETLT, MVT::i32), MVT::i32),
-      r1, DAG.getConstant(0, OVT));
+  SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
 
   // iadd r0, r0, r10
   r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);