diff options
| author | Tom Stellard <[email protected]> | 2012-07-18 12:26:45 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-07-27 17:08:06 +0000 |
| commit | 92823fb72abf1539bdb545fedc5525e9fc0b04cc (patch) | |
| tree | 185010806f0eb46a12a53b09b1998c5089d3974c /src/gallium/drivers/radeon/AMDILISelLowering.cpp | |
| parent | 46d12c99a24cebe01cd00575b39961231dec47c8 (diff) | |
radeon/llvm: Move lowering of SETCC node to R600ISelLowering
SI will handle SETCC different from R600, so we need to move it
out of the shared instruction selector.
Diffstat (limited to 'src/gallium/drivers/radeon/AMDILISelLowering.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILISelLowering.cpp | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp index b36fe42af9b..42a9680e2e2 100644 --- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp @@ -520,7 +520,6 @@ AMDILTargetLowering::LowerMemArgument( setOperationAction(ISD::SUBC, VT, Expand); setOperationAction(ISD::ADDE, VT, Expand); setOperationAction(ISD::ADDC, VT, Expand); - setOperationAction(ISD::SETCC, VT, Custom); setOperationAction(ISD::BRCOND, VT, Custom); setOperationAction(ISD::BR_CC, VT, Custom); setOperationAction(ISD::BR_JT, VT, Expand); @@ -581,7 +580,6 @@ AMDILTargetLowering::LowerMemArgument( setOperationAction(ISD::SDIVREM, VT, Expand); setOperationAction(ISD::SMUL_LOHI, VT, Expand); // setOperationAction(ISD::VSETCC, VT, Expand); - setOperationAction(ISD::SETCC, VT, Expand); setOperationAction(ISD::SELECT_CC, VT, Expand); setOperationAction(ISD::SELECT, VT, Expand); @@ -632,7 +630,6 @@ AMDILTargetLowering::LowerMemArgument( setOperationAction(ISD::BR_CC, MVT::Other, Custom); setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::BRIND, MVT::Other, Expand); - setOperationAction(ISD::SETCC, MVT::Other, Custom); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::Other, Custom); @@ -849,7 +846,6 @@ AMDILTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const LOWER(SREM); LOWER(BUILD_VECTOR); LOWER(SELECT); - LOWER(SETCC); LOWER(SIGN_EXTEND_INREG); LOWER(DYNAMIC_STACKALLOC); LOWER(BRCOND); @@ -1362,37 +1358,6 @@ AMDILTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const Op.getValueType(), Cond, LHS, RHS); return Cond; } -SDValue -AMDILTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const -{ - SDValue Cond; - SDValue LHS = Op.getOperand(0); - SDValue RHS = Op.getOperand(1); - SDValue CC = Op.getOperand(2); - DebugLoc DL = Op.getDebugLoc(); - ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); - unsigned int AMDILCC = CondCCodeToCC( - SetCCOpcode, - LHS.getValueType().getSimpleVT().SimpleTy); - assert((AMDILCC != AMDILCC::COND_ERROR) && "Invalid SetCC!"); - assert(Op.getValueType() == MVT::i32); - Cond = DAG.getNode( - ISD::SELECT_CC, - Op.getDebugLoc(), - MVT::i32, - LHS, RHS, - DAG.getConstant(-1, MVT::i32), - DAG.getConstant(0, MVT::i32), - CC); - Cond = getConversionNode(DAG, Cond, Op, true); - Cond = DAG.getNode( - ISD::AND, - DL, - Cond.getValueType(), - DAG.getConstant(1, Cond.getValueType()), - Cond); - return Cond; -} SDValue AMDILTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const |