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authorGert Wollny <[email protected]>2018-06-01 01:20:54 +0200
committerDave Airlie <[email protected]>2018-06-25 05:40:19 +0100
commiteebb65258d15af2b2fc50d3b64b5d2eafbffcb47 (patch)
treeca8cd29d9dab0748c5c9489a4f53efd2d7a97271 /src/gallium/drivers/r600
parentcd7db0ab0a871b34d6d07a1db9d3b8b4b8342b35 (diff)
r600/sb: give the scheduler more margin to find valid instructions groups
For instruction sequences that change the address register with every load the current limit to bail out of the scheduler and reject the optimisation was too tight, i.e. it was expected that at least one pending instruction would be scheduled each time. Give the scheduler more margin to sort out these load sequences by allowing a number of rounds where no instruction is scheduled. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106163 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600')
-rw-r--r--src/gallium/drivers/r600/sb/sb_sched.cpp13
1 files changed, 10 insertions, 3 deletions
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp b/src/gallium/drivers/r600/sb/sb_sched.cpp
index ffc66018b10..fe887c84c70 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.cpp
+++ b/src/gallium/drivers/r600/sb/sb_sched.cpp
@@ -1154,14 +1154,21 @@ bool post_scheduler::schedule_alu(container_node *c) {
assert(!ready.empty() || !ready_copies.empty());
- bool improving = true;
+ /* This number is rather arbitrary, important is that the scheduler has
+ * more than one try to create an instruction group
+ */
+ int improving = 10;
int last_pending = pending.count();
- while (improving) {
+ while (improving > 0) {
prev_regmap = regmap;
if (!prepare_alu_group()) {
int new_pending = pending.count();
- improving = (new_pending < last_pending) || (last_pending == 0);
+ if ((new_pending < last_pending) || (last_pending == 0))
+ improving = 10;
+ else
+ --improving;
+
last_pending = new_pending;
if (alu.current_idx[0] || alu.current_idx[1]) {