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authorDave Airlie <[email protected]>2017-12-04 05:31:46 +1000
committerDave Airlie <[email protected]>2018-01-29 05:42:28 +1000
commit1c9ea24a19a28e87f6038281c516287f25ad88b5 (patch)
treef59e78bd4516fc09ee7133de40c2dfa6fe5eb7e3 /src/gallium/drivers/r600/r600_pipe_common.h
parenta7ec366e503cc2b05d6920fa5027b0f001ae9e58 (diff)
r600: add ARB_query_buffer_object support
This uses a different shader than radeonsi, as we can't address non-256 aligned ssbos, which the radeonsi code does. This passes some extra offsets into the shader. It also contains a set of u64 instruction implementation that may or may not be complete (at least the u64div is definitely not something that works outside this use-case). If r600 grows 64-bit integers, it will use the GLSL lowering for divmod. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r600_pipe_common.h')
-rw-r--r--src/gallium/drivers/r600/r600_pipe_common.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/r600/r600_pipe_common.h b/src/gallium/drivers/r600/r600_pipe_common.h
index 1fdbc39a560..86a20f8639b 100644
--- a/src/gallium/drivers/r600/r600_pipe_common.h
+++ b/src/gallium/drivers/r600/r600_pipe_common.h
@@ -679,6 +679,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx,
uint32_t new_fence, unsigned query_type);
unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
void r600_gfx_wait_fence(struct r600_common_context *ctx,
+ struct r600_resource *buf,
uint64_t va, uint32_t ref, uint32_t mask);
void r600_draw_rectangle(struct blitter_context *blitter,
void *vertex_elements_cso,