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authorJerome Glisse <[email protected]>2012-10-11 10:40:30 -0400
committerJerome Glisse <[email protected]>2012-12-20 18:23:51 -0500
commit6532eb17baff6e61b427f29e076883f8941ae664 (patch)
tree8a2fbc76f6037381017d81148996a4db6598254a /src/gallium/drivers/r600/r600_pipe.h
parent24b1206ab2dcd506aaac3ef656aebc8bc20cd27a (diff)
r600g: add htile support v16
htile is used for HiZ and HiS support and fast Z/S clears. This commit just adds the htile setup and Fast Z clear. We don't take full advantage of HiS with that patch. v2 really use fast clear, still random issue with some tiles need to try more flush combination, fix depth/stencil texture decompression v3 fix random issue on r6xx/r7xx v4 rebase on top of lastest mesa, disable CB export when clearing htile surface to avoid wasting bandwidth v5 resummarize htile surface when uploading z value. Fix z/stencil decompression, the custom blitter with custom dsa is no longer needed. v6 Reorganize render control/override update mecanism, fixing more issues in the process. v7 Add nop after depth surface base update to work around some htile flushing issue. For htile to 8x8 on r6xx/r7xx as other combination have issue. Do not enable hyperz when flushing/uncompressing depth buffer. v8 Fix htile surface, preload and prefetch setup. Only set preload and prefetch on htile surface clear like fglrx. Record depth clear value per level. Support several level for the htile surface. First depth clear can't be a fast clear. v9 Fix comments, properly account new register in emit function, disable fast zclear if clearing different layer of texture array to different value v10 Disable hyperz for texture array making test simpler. Force db_misc_state update when no depth buffer is bound. Remove unused variable, rename depth_clearstencil to depth_clear. Don't allocate htile surface for flushed depth. Something broken the cliprect change, this need to be investigated. v11 Rebase on top of newer mesa v12 Rebase on top of newer mesa v13 Rebase on top of newer mesa, htile surface need to be initialized to zero, somehow special casing first clear to not use fast clear and thus initialize the htile surface with proper value does not work in all case. v14 Use resource not texture for htile buffer make the htile buffer size computation easier and simpler. Disable preload on evergreen as its still troublesome in some case v15 Cleanup some comment and remove some left over v16 Define name for bit 20 of CP_COHER_CNTL Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Jerome Glisse <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r600_pipe.h')
-rw-r--r--src/gallium/drivers/r600/r600_pipe.h26
1 files changed, 17 insertions, 9 deletions
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 8df50e9bc83..515174a2e6e 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -35,7 +35,7 @@
#include "r600_resource.h"
#include "evergreen_compute.h"
-#define R600_NUM_ATOMS 36
+#define R600_NUM_ATOMS 37
#define R600_MAX_USER_CONST_BUFFERS 1
#define R600_MAX_DRIVER_CONST_BUFFERS 2
@@ -77,15 +77,21 @@ struct r600_command_buffer {
unsigned pkt_flags;
};
+struct r600_db_state {
+ struct r600_atom atom;
+ struct r600_surface *rsurf;
+};
+
struct r600_db_misc_state {
- struct r600_atom atom;
- bool occlusion_query_enabled;
- bool flush_depthstencil_through_cb;
- bool flush_depthstencil_in_place;
- bool copy_depth, copy_stencil;
- unsigned copy_sample;
- unsigned log_samples;
- unsigned db_shader_control;
+ struct r600_atom atom;
+ bool occlusion_query_enabled;
+ bool flush_depthstencil_through_cb;
+ bool flush_depthstencil_in_place;
+ bool copy_depth, copy_stencil;
+ unsigned copy_sample;
+ unsigned log_samples;
+ unsigned db_shader_control;
+ bool htile_clear;
};
struct r600_cb_misc_state {
@@ -220,6 +226,7 @@ struct r600_screen {
bool has_streamout;
bool has_msaa;
enum r600_msaa_texture_mode msaa_texture_support;
+ bool use_hyperz;
struct r600_tiling_info tiling_info;
struct r600_pipe_fences fences;
@@ -439,6 +446,7 @@ struct r600_context {
struct r600_clip_misc_state clip_misc_state;
struct r600_clip_state clip_state;
struct r600_db_misc_state db_misc_state;
+ struct r600_db_state db_state;
struct r600_cso_state dsa_state;
struct r600_framebuffer framebuffer;
struct r600_poly_offset_state poly_offset_state;