r600g: implement MSAA for r700

Reviewed-by: Jerome Glisse <[email protected]>

1 files changed, 16 insertions, 0 deletions

diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index d0b453ac7c0..7b7b6b1ffac 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -240,6 +240,10 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 /* R600/R700 configuration */
 static const struct r600_reg r600_config_reg_list[] = {
 	{R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
+	{R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, 0, 0},
+	{R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, 0, 0},
+	{R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 0, 0},
+	{R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, 0, 0},
 	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
 };
 
@@ -260,6 +264,7 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{R_028100_CB_COLOR0_MASK, 0, 0},
 	{R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
@@ -269,6 +274,7 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0},
+	{R_028104_CB_COLOR1_MASK, 0, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
@@ -279,6 +285,7 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0},
+	{R_028108_CB_COLOR2_MASK, 0, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
@@ -289,6 +296,7 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0},
+	{R_02810C_CB_COLOR3_MASK, 0, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
@@ -299,6 +307,7 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0},
+	{R_028110_CB_COLOR4_MASK, 0, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
@@ -309,6 +318,7 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0},
+	{R_028114_CB_COLOR5_MASK, 0, 0},
 	{R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)},
 	{R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
 	{R_028078_CB_COLOR6_SIZE, 0, 0},
@@ -317,6 +327,7 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0},
+	{R_028118_CB_COLOR6_MASK, 0, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
 	{R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)},
 	{GROUP_FORCE_NEW_BLOCK, 0, 0},
@@ -325,6 +336,7 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_02809C_CB_COLOR7_VIEW, 0, 0},
 	{R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0},
 	{R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0},
+	{R_02811C_CB_COLOR7_MASK, 0, 0},
 	{R_028120_CB_CLEAR_RED, 0, 0},
 	{R_028124_CB_CLEAR_GREEN, 0, 0},
 	{R_028128_CB_CLEAR_BLUE, 0, 0},
@@ -377,6 +389,8 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_028A04_PA_SU_POINT_MINMAX, 0, 0},
 	{R_028A08_PA_SU_LINE_CNTL, 0, 0},
 	{R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
+	{R_028C00_PA_SC_LINE_CNTL, 0, 0},
+	{R_028C04_PA_SC_AA_CONFIG, 0, 0},
 	{R_028C08_PA_SU_VTX_CNTL, 0, 0},
 	{R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
 	{R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
@@ -504,6 +518,8 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_028408_VGT_INDX_OFFSET, 0, 0},
 	{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
 	{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
+	{R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0},
+	{R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0},
 };
 
 static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)