r600g: fix evergreen depth flushing.

although evergreen can apparantly sample direct from 24-bit,
just make it work with the current method for now.

1 files changed, 44 insertions, 8 deletions

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 64fadb16e0b..5775b04cc7a 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -440,14 +440,11 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 	bo[1] = rbuffer->bo;
 	/* FIXME depth texture decompression */
 	if (tmp->depth) {
-#if 0
-		r = evergreen_texture_from_depth(ctx, tmp, view->first_level);
-		if (r) {
-			return;
-		}
-		bo[0] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
-		bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
-#endif
+		r600_texture_depth_flush(ctx, texture);
+		tmp = (struct r600_resource_texture*)texture;
+		rbuffer = &tmp->flushed_depth_texture->resource;
+		bo[0] = rbuffer->bo;
+		bo[1] = rbuffer->bo;
 	}
 	pitch = align(tmp->pitch[0] / tmp->bpt, 8);
 
@@ -852,6 +849,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 	}
 	pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
 	rctx->framebuffer = *state;
+	rctx->pframebuffer = &rctx->framebuffer;
 
 	/* build states */
 	for (int i = 0; i < state->nr_cbufs; i++) {
@@ -1645,3 +1643,41 @@ void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader
 			R_0288A4_SQ_PGM_START_FS,
 			0x00000000, 0xFFFFFFFF, shader->bo);
 }
+
+void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
+{
+	struct pipe_depth_stencil_alpha_state dsa;
+	struct r600_pipe_state *rstate;
+	boolean quirk = false;
+
+	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
+		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
+		quirk = true;
+
+	memset(&dsa, 0, sizeof(dsa));
+
+	if (quirk) {
+		dsa.depth.enabled = 1;
+		dsa.depth.func = PIPE_FUNC_LEQUAL;
+		dsa.stencil[0].enabled = 1;
+		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
+		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
+		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
+		dsa.stencil[0].writemask = 0xff;
+	}
+
+	rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
+	r600_pipe_state_add_reg(rstate,
+				R_02880C_DB_SHADER_CONTROL,
+				0x0,
+				S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028000_DB_RENDER_CONTROL,
+				S_028000_DEPTH_COPY_ENABLE(1) |
+				S_028000_STENCIL_COPY_ENABLE(1) |
+				S_028000_COPY_CENTROID(1),
+				S_028000_DEPTH_COPY_ENABLE(1) |
+				S_028000_STENCIL_COPY_ENABLE(1) |
+				S_028000_COPY_CENTROID(1), NULL);
+	return rstate;
+}