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authorErico Nunes <[email protected]>2019-08-28 01:07:55 +0200
committerErico Nunes <[email protected]>2019-09-05 23:29:24 +0000
commit7b2f195d0b34332c2ed0d6550f839cb1922caf0c (patch)
tree69099baf50dd0ac3e73a29124f5dd71e167b656e /src/gallium/drivers/lima/lima_resource.c
parentf9bf1a95ecbd24e9f02a5e67f6959ccf08eba1d1 (diff)
lima/ppir: optimizations in regalloc spilling code
Avoid creating unnecessary instructions for the load/store temp nodes when not required, to further reduce register pressure. The store_temp operation seems to be unable to do any spilling. At least the offline shader seems to never output instructions accessing swizzled components, and attempting to output that in ppir results in errors. So, force spilled registers to allocate a full vec4 register. This seems to be the optimal way as it is possible to always keep stores and temps in a single instruction that can be pipelined. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]>
Diffstat (limited to 'src/gallium/drivers/lima/lima_resource.c')
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