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authorChris Wilson <[email protected]>2019-02-22 20:53:41 +0000
committerKenneth Graunke <[email protected]>2019-03-13 10:54:16 -0700
commit97ad0efba08d336813366b9cab114c94c2ca61db (patch)
treed12a2a12d902f0721322dcd0adecae35277a0ef0 /src/gallium/drivers/iris
parent797fb6c6ac96cb7d1d5f9a04dc4f22f350093a16 (diff)
iris: Use streaming loads to read from tiled surfaces
Always use the streaming load (since we know we have Broadwell+, all of our target CPU support sse41) for reading back form the tiled surface for mapping the resource. This means we hit the fast WC handling paths on Atoms (without LLC), and for big Core (with LLC) using the streaming load is no less efficient as we do not require the tiled buffer to be pulled into the CPU cache. Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/gallium/drivers/iris')
-rw-r--r--src/gallium/drivers/iris/iris_bufmgr.c5
-rw-r--r--src/gallium/drivers/iris/iris_resource.c2
2 files changed, 5 insertions, 2 deletions
diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c
index b20297fd94a..ae335163d45 100644
--- a/src/gallium/drivers/iris/iris_bufmgr.c
+++ b/src/gallium/drivers/iris/iris_bufmgr.c
@@ -1186,8 +1186,11 @@ can_map_cpu(struct iris_bo *bo, unsigned flags)
* most drawing while non-persistent mappings are active, we may still use
* the GPU for blits or other operations, causing batches to happen at
* inconvenient times.
+ *
+ * If RAW is set, we expect the caller to be able to handle a WC buffer
+ * more efficiently than the involuntary clflushes.
*/
- if (flags & (MAP_PERSISTENT | MAP_COHERENT | MAP_ASYNC))
+ if (flags & (MAP_PERSISTENT | MAP_COHERENT | MAP_ASYNC | MAP_RAW))
return false;
return !(flags & MAP_WRITE);
diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
index 155c8786d27..acb19364a3b 100644
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -1143,7 +1143,7 @@ iris_map_tiled_memcpy(struct iris_transfer *map)
isl_memcpy_tiled_to_linear(x1, x2, y1, y2, ptr, src, xfer->stride,
surf->row_pitch_B, has_swizzling,
- surf->tiling, ISL_MEMCPY);
+ surf->tiling, ISL_MEMCPY_STREAMING_LOAD);
box.z++;
}
}