ilo: rename ilo_resource to ilo_texture

In preparation for the introduction of ilo_buffer.

1 files changed, 34 insertions, 34 deletions

diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen7.c b/src/gallium/drivers/ilo/ilo_gpe_gen7.c
index b703a69779b..27fa1243803 100644
--- a/src/gallium/drivers/ilo/ilo_gpe_gen7.c
+++ b/src/gallium/drivers/ilo/ilo_gpe_gen7.c
@@ -1130,7 +1130,7 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
 {
    const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x18);
    const uint8_t cmd_len = 4;
-   struct ilo_resource *res;
+   struct ilo_texture *tex;
    int end;
 
    ILO_GPE_VALID_GEN(dev, 7, 7);
@@ -1145,7 +1145,7 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
       return;
    }
 
-   res = ilo_resource(so_target->buffer);
+   tex = ilo_texture(so_target->buffer);
 
    /* DWord-aligned */
    assert(stride % 4 == 0 && base % 4 == 0);
@@ -1159,8 +1159,8 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
    ilo_cp_write(cp, cmd | (cmd_len - 2));
    ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT |
                     stride);
-   ilo_cp_write_bo(cp, base, res->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
-   ilo_cp_write_bo(cp, end, res->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+   ilo_cp_write_bo(cp, base, tex->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+   ilo_cp_write_bo(cp, end, tex->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
    ilo_cp_end(cp);
 }
 
@@ -1296,7 +1296,7 @@ gen7_fill_null_SURFACE_STATE(const struct ilo_dev_info *dev,
 
 static void
 gen7_fill_buffer_SURFACE_STATE(const struct ilo_dev_info *dev,
-                               const struct ilo_resource *res,
+                               const struct ilo_texture *tex,
                                unsigned offset, unsigned size,
                                unsigned struct_size,
                                enum pipe_format elem_format,
@@ -1380,7 +1380,7 @@ gen7_fill_buffer_SURFACE_STATE(const struct ilo_dev_info *dev,
     *     "If Surface Type is SURFTYPE_BUFFER, this field (Tiled Surface) must
     *      be false (because buffers are supported only in linear memory)."
     */
-   assert(res->tiling == INTEL_TILING_NONE);
+   assert(tex->tiling == INTEL_TILING_NONE);
 
    pitch--;
    num_entries--;
@@ -1415,7 +1415,7 @@ gen7_fill_buffer_SURFACE_STATE(const struct ilo_dev_info *dev,
 
 static void
 gen7_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
-                               struct ilo_resource *res,
+                               struct ilo_texture *tex,
                                enum pipe_format format,
                                unsigned first_level, unsigned num_levels,
                                unsigned first_layer, unsigned num_layers,
@@ -1429,7 +1429,7 @@ gen7_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
    ILO_GPE_VALID_GEN(dev, 7, 7);
    assert(num_dwords == 8);
 
-   surface_type = ilo_gpe_gen6_translate_texture(res->base.target);
+   surface_type = ilo_gpe_gen6_translate_texture(tex->base.target);
    assert(surface_type != BRW_SURFACE_BUFFER);
 
    if (is_rt)
@@ -1438,13 +1438,13 @@ gen7_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
       surface_format = ilo_translate_texture_format(format);
    assert(surface_format >= 0);
 
-   width = res->base.width0;
-   height = res->base.height0;
-   pitch = res->bo_stride;
+   width = tex->base.width0;
+   height = tex->base.height0;
+   pitch = tex->bo_stride;
 
-   switch (res->base.target) {
+   switch (tex->base.target) {
    case PIPE_TEXTURE_3D:
-      depth = res->base.depth0;
+      depth = tex->base.depth0;
       break;
    case PIPE_TEXTURE_CUBE:
    case PIPE_TEXTURE_CUBE_ARRAY:
@@ -1503,7 +1503,7 @@ gen7_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
       /* we lose the capability for layered rendering */
       assert(num_levels == 1 && num_layers == 1);
 
-      layer_offset = ilo_resource_get_slice_offset(res,
+      layer_offset = ilo_texture_get_slice_offset(tex,
             first_level, first_layer, true, &x_offset, &y_offset);
 
       assert(x_offset % 4 == 0);
@@ -1512,10 +1512,10 @@ gen7_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
       y_offset /= 2;
 
       /* derive the size for the LOD */
-      width = u_minify(res->base.width0, first_level);
-      height = u_minify(res->base.height0, first_level);
+      width = u_minify(tex->base.width0, first_level);
+      height = u_minify(tex->base.height0, first_level);
       if (surface_type == BRW_SURFACE_3D)
-         depth = u_minify(res->base.depth0, first_level);
+         depth = u_minify(tex->base.depth0, first_level);
 
       first_level = 0;
       first_layer = 0;
@@ -1551,7 +1551,7 @@ gen7_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
     *
     *     "For linear surfaces, this field (X Offset) must be zero."
     */
-   if (res->tiling == INTEL_TILING_NONE) {
+   if (tex->tiling == INTEL_TILING_NONE) {
       if (is_rt) {
          const int elem_size = util_format_get_blocksize(format);
          assert(layer_offset % elem_size == 0);
@@ -1563,18 +1563,18 @@ gen7_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
 
    dw[0] = surface_type << BRW_SURFACE_TYPE_SHIFT |
            surface_format << BRW_SURFACE_FORMAT_SHIFT |
-           ilo_gpe_gen6_translate_winsys_tiling(res->tiling) << 13;
+           ilo_gpe_gen6_translate_winsys_tiling(tex->tiling) << 13;
 
    if (surface_type != BRW_SURFACE_3D && depth > 1)
       dw[0] |= GEN7_SURFACE_IS_ARRAY;
 
-   if (res->valign_4)
+   if (tex->valign_4)
       dw[0] |= GEN7_SURFACE_VALIGN_4;
 
-   if (res->halign_8)
+   if (tex->halign_8)
       dw[0] |= GEN7_SURFACE_HALIGN_8;
 
-   if (res->array_spacing_full)
+   if (tex->array_spacing_full)
       dw[0] |= GEN7_SURFACE_ARYSPC_FULL;
    else
       dw[0] |= GEN7_SURFACE_ARYSPC_LOD0;
@@ -1601,7 +1601,7 @@ gen7_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
     * means the samples are interleaved.  The layouts are the same when the
     * number of samples is 1.
     */
-   if (res->interleaved && res->base.nr_samples > 1) {
+   if (tex->interleaved && tex->base.nr_samples > 1) {
       assert(!is_rt);
       dw[4] |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
    }
@@ -1609,9 +1609,9 @@ gen7_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
       dw[4] |= GEN7_SURFACE_MSFMT_MSS;
    }
 
-   if (res->base.nr_samples > 4)
+   if (tex->base.nr_samples > 4)
       dw[4] |= GEN7_SURFACE_MULTISAMPLECOUNT_8;
-   else if (res->base.nr_samples > 2)
+   else if (tex->base.nr_samples > 2)
       dw[4] |= GEN7_SURFACE_MULTISAMPLECOUNT_4;
    else
       dw[4] |= GEN7_SURFACE_MULTISAMPLECOUNT_1;
@@ -1673,15 +1673,15 @@ gen7_emit_surf_SURFACE_STATE(const struct ilo_dev_info *dev,
    ILO_GPE_VALID_GEN(dev, 7, 7);
 
    if (surface && surface->texture) {
-      struct ilo_resource *res = ilo_resource(surface->texture);
+      struct ilo_texture *tex = ilo_texture(surface->texture);
 
-      bo = res->bo;
+      bo = tex->bo;
 
       /*
        * classic i965 sets render_cache_rw for constant buffers and sol
        * surfaces but not render buffers.  Why?
        */
-      gen7_fill_normal_SURFACE_STATE(dev, res, surface->format,
+      gen7_fill_normal_SURFACE_STATE(dev, tex, surface->format,
             surface->u.tex.level, 1,
             surface->u.tex.first_layer,
             surface->u.tex.last_layer - surface->u.tex.first_layer + 1,
@@ -1701,19 +1701,19 @@ gen7_emit_view_SURFACE_STATE(const struct ilo_dev_info *dev,
                              const struct pipe_sampler_view *view,
                              struct ilo_cp *cp)
 {
-   struct ilo_resource *res = ilo_resource(view->texture);
+   struct ilo_texture *tex = ilo_texture(view->texture);
    uint32_t dw[8];
 
    ILO_GPE_VALID_GEN(dev, 7, 7);
 
-   gen7_fill_normal_SURFACE_STATE(dev, res, view->format,
+   gen7_fill_normal_SURFACE_STATE(dev, tex, view->format,
          view->u.tex.first_level,
          view->u.tex.last_level - view->u.tex.first_level + 1,
          view->u.tex.first_layer,
          view->u.tex.last_layer - view->u.tex.first_layer + 1,
          false, false, dw, Elements(dw));
 
-   return gen7_emit_SURFACE_STATE(dev, res->bo, false, dw, Elements(dw), cp);
+   return gen7_emit_SURFACE_STATE(dev, tex->bo, false, dw, Elements(dw), cp);
 }
 
 static uint32_t
@@ -1722,17 +1722,17 @@ gen7_emit_cbuf_SURFACE_STATE(const struct ilo_dev_info *dev,
                              struct ilo_cp *cp)
 {
    const enum pipe_format elem_format = PIPE_FORMAT_R32G32B32A32_FLOAT;
-   struct ilo_resource *res = ilo_resource(cbuf->buffer);
+   struct ilo_texture *tex = ilo_texture(cbuf->buffer);
    uint32_t dw[8];
 
    ILO_GPE_VALID_GEN(dev, 7, 7);
 
-   gen7_fill_buffer_SURFACE_STATE(dev, res,
+   gen7_fill_buffer_SURFACE_STATE(dev, tex,
          cbuf->buffer_offset, cbuf->buffer_size,
          util_format_get_blocksize(elem_format), elem_format,
          false, false, dw, Elements(dw));
 
-   return gen7_emit_SURFACE_STATE(dev, res->bo, false, dw, Elements(dw), cp);
+   return gen7_emit_SURFACE_STATE(dev, tex->bo, false, dw, Elements(dw), cp);
 }
 
 static uint32_t