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authorRob Clark <[email protected]>2016-01-15 17:07:02 -0500
committerRob Clark <[email protected]>2016-01-16 14:22:43 -0500
commitddede497b831fb98e3540247b570968532cdacc9 (patch)
treefb8a6e63ab36285a42f07a63de8b9ab63ec8eb22 /src/gallium/drivers/freedreno/ir3/ir3_cp.c
parentebd3a1fc17977a487b0ed86294e9b8312a1bf335 (diff)
freedreno/ir3: workaround bug/feature
Seems like in certain cases, we cannot use c<a0.x+0> as the third src to cat3 instructions. This may be slightly conservative, we may only have this restriction when the first src is also const. This fixes, for example, +24/-0 of the variable-indexing piglit tests. Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno/ir3/ir3_cp.c')
-rw-r--r--src/gallium/drivers/freedreno/ir3/ir3_cp.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cp.c b/src/gallium/drivers/freedreno/ir3/ir3_cp.c
index 0d88e7bc3ab..1cc211a7663 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cp.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cp.c
@@ -288,6 +288,15 @@ reg_cp(struct ir3_instruction *instr, struct ir3_register *reg, unsigned n)
conflicts(instr->address, reg->instr->address))
return;
+ /* This seems to be a hw bug, or something where the timings
+ * just somehow don't work out. This restriction may only
+ * apply if the first src is also CONST.
+ */
+ if ((instr->category == 3) && (n == 2) &&
+ (src_reg->flags & IR3_REG_RELATIV) &&
+ (src_reg->array.offset == 0))
+ return;
+
src_reg = ir3_reg_clone(instr->block->shader, src_reg);
src_reg->flags = new_flags;
instr->regs[n+1] = src_reg;