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authorRob Clark <[email protected]>2017-12-31 15:01:51 -0500
committerRob Clark <[email protected]>2018-01-14 16:13:39 -0500
commit39b63c18f1a838d57458ceb99ca58d3c0257c402 (patch)
tree8c91e3bae7d3839ef6ab59816ddfa7ee47e6ffd4 /src/gallium/drivers/freedreno/freedreno_resource.h
parent868b02cfb431cbccd2b7d54bdc89100eb7af71b5 (diff)
freedreno/a5xx: texture tiling
Overall a nice 5-10% gain for most games. And more for things like glmark2 texture benchmark. There are some rough edges. In particular, the hardware seems to only support tiling or component swap. (Ie. from hw PoV, ARGB/ABGR/RGBA/ BGRA are all the same format but with different component swap.) For tiled formats, only ARGB is possible. This isn't a big problem for *sampling* since we also have swizzle state there (and since util_format_compose_swizzles() already takes into account the component order, we didn't use COLOR_SWAP for sampling). But it is a problem if you try to render to a tiled BGRA (for example) surface. The next patch introduces a workaround for blitter, so we can generate tiled textures in ABGR/RGBA/BGRA, but that doesn't help the render- target case. To handle that, I think we'd need to keep track that the tiled format is different from the linear format, which seems like it would get extra fun with sampler views/etc. So for now, disabled by default, enable with FD_MESA_DEBUG=ttile. In practice it works fine for all the games I've tried, but makes piglit grumpy. Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno/freedreno_resource.h')
-rw-r--r--src/gallium/drivers/freedreno/freedreno_resource.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.h b/src/gallium/drivers/freedreno/freedreno_resource.h
index 0b41a13be33..2834969110b 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.h
+++ b/src/gallium/drivers/freedreno/freedreno_resource.h
@@ -97,6 +97,9 @@ struct fd_resource {
*/
uint32_t bc_batch_mask;
+ unsigned tile_mode : 2;
+ unsigned preferred_tile_mode : 2;
+
/*
* LRZ
*/
@@ -164,6 +167,16 @@ fd_resource_offset(struct fd_resource *rsc, unsigned level, unsigned layer)
return offset;
}
+/* This might be a5xx specific, but higher mipmap levels are always linear: */
+static inline bool
+fd_resource_level_linear(struct pipe_resource *prsc, int level)
+{
+ unsigned w = u_minify(prsc->width0, level);
+ if (w < 16)
+ return true;
+ return false;
+}
+
void fd_blitter_pipe_begin(struct fd_context *ctx, bool render_cond, bool discard,
enum fd_render_stage stage);
void fd_blitter_pipe_end(struct fd_context *ctx);