freedreno/a5xx: texture tiling

Overall a nice 5-10% gain for most games.  And more for things like
glmark2 texture benchmark.

There are some rough edges.  In particular, the hardware seems to only
support tiling or component swap.  (Ie. from hw PoV, ARGB/ABGR/RGBA/
BGRA are all the same format but with different component swap.)  For
tiled formats, only ARGB is possible.  This isn't a big problem for
*sampling* since we also have swizzle state there (and since
util_format_compose_swizzles() already takes into account the component
order, we didn't use COLOR_SWAP for sampling).  But it is a problem if
you try to render to a tiled BGRA (for example) surface.

The next patch introduces a workaround for blitter, so we can generate
tiled textures in ABGR/RGBA/BGRA, but that doesn't help the render-
target case.  To handle that, I think we'd need to keep track that the
tiled format is different from the linear format, which seems like it
would get extra fun with sampler views/etc.

So for now, disabled by default, enable with FD_MESA_DEBUG=ttile.  In
practice it works fine for all the games I've tried, but makes piglit
grumpy.

Signed-off-by: Rob Clark <[email protected]>

1 files changed, 16 insertions, 8 deletions

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
index e16ed1afa11..ae73bc181ba 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
@@ -49,12 +49,6 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 	enum a5xx_tile_mode tile_mode;
 	unsigned i;
 
-	if (gmem) {
-		tile_mode = TILE5_2;
-	} else {
-		tile_mode = TILE5_LINEAR;
-	}
-
 	for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
 		enum a5xx_color_fmt format = 0;
 		enum a3xx_color_swap swap = WZYX;
@@ -66,6 +60,12 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 		uint32_t base = 0;
 		uint32_t offset = 0;
 
+		if (gmem) {
+			tile_mode = TILE5_2;
+		} else {
+			tile_mode = TILE5_LINEAR;
+		}
+
 		if ((i < nr_bufs) && bufs[i]) {
 			struct pipe_surface *psurf = bufs[i];
 			enum pipe_format pformat = psurf->format;
@@ -91,6 +91,9 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 			} else {
 				stride = slice->pitch * rsc->cpp;
 				size = slice->size0;
+
+				if (!fd_resource_level_linear(psurf->texture, psurf->u.tex.level))
+					tile_mode = rsc->tile_mode;
 			}
 		}
 
@@ -488,7 +491,7 @@ emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
 
 		OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
 		OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
-				A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) |
+				A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(rsc->tile_mode) |
 				A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
 		OUT_RING(ring, A5XX_RB_MRT_PITCH(slice->pitch * rsc->cpp));
 		OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(slice->size0));
@@ -606,6 +609,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
 	struct fd_ringbuffer *ring = batch->gmem;
 	struct fd_resource *rsc = fd_resource(psurf->texture);
 	struct fd_resource_slice *slice;
+	bool tiled;
 	uint32_t offset;
 
 	if (buf == BLIT_S)
@@ -623,8 +627,12 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
 	OUT_RING(ring, 0x00000000);   /* RB_BLIT_FLAG_DST_PITCH */
 	OUT_RING(ring, 0x00000000);   /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
 
+	tiled = rsc->tile_mode &&
+		!fd_resource_level_linear(psurf->texture, psurf->u.tex.level);
+
 	OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
-	OUT_RING(ring, 0x00000004);   /* XXX RB_RESOLVE_CNTL_3 */
+	OUT_RING(ring, 0x00000004 |   /* XXX RB_RESOLVE_CNTL_3 */
+			COND(tiled, A5XX_RB_RESOLVE_CNTL_3_TILED));
 	OUT_RELOCW(ring, rsc->bo, offset, 0, 0);     /* RB_BLIT_DST_LO/HI */
 	OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(slice->pitch * rsc->cpp));
 	OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(slice->size0));