diff options
| author | Christian GMEINER <[email protected]> | 2019-08-19 17:07:29 +0200 |
|---|---|---|
| committer | Christian Gmeiner <[email protected]> | 2019-08-19 22:36:45 +0200 |
| commit | 7492685b1be0f1300ba910de07d0f409bddf3be3 (patch) | |
| tree | 61496d136cf87ed034a9ad1429db75a52913034c /src/gallium/drivers/etnaviv/hw/state_3d.xml.h | |
| parent | 1395503424391db4aba05bd68a8288f426992d56 (diff) | |
etnaviv: update headers from rnndb
Update to etna_viv commit c51353e.
Signed-off-by: Christian GMEINER <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Reviewed-by: Jonathan Marek <[email protected]>
Diffstat (limited to 'src/gallium/drivers/etnaviv/hw/state_3d.xml.h')
| -rw-r--r-- | src/gallium/drivers/etnaviv/hw/state_3d.xml.h | 139 |
1 files changed, 102 insertions, 37 deletions
diff --git a/src/gallium/drivers/etnaviv/hw/state_3d.xml.h b/src/gallium/drivers/etnaviv/hw/state_3d.xml.h index f7adf514875..222a3aa54a6 100644 --- a/src/gallium/drivers/etnaviv/hw/state_3d.xml.h +++ b/src/gallium/drivers/etnaviv/hw/state_3d.xml.h @@ -8,15 +8,15 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 26087 bytes, from 2019-07-31 15:09:17) -- common.xml ( 35468 bytes, from 2019-06-10 23:29:22) -- common_3d.xml ( 14988 bytes, from 2019-07-15 12:48:57) -- state_hi.xml ( 30232 bytes, from 2019-06-10 23:29:22) -- copyright.xml ( 1597 bytes, from 2019-06-10 23:29:22) -- state_2d.xml ( 51552 bytes, from 2019-06-10 23:29:22) -- state_3d.xml ( 80519 bytes, from 2019-07-31 15:09:17) -- state_blt.xml ( 13381 bytes, from 2019-07-04 11:45:35) -- state_vg.xml ( 5975 bytes, from 2019-06-10 23:29:22) +- state.xml ( 26666 bytes, from 2019-08-19 14:35:07) +- common.xml ( 35468 bytes, from 2019-01-07 09:52:31) +- common_3d.xml ( 14322 bytes, from 2019-08-19 14:35:07) +- state_hi.xml ( 30232 bytes, from 2019-01-07 09:52:31) +- copyright.xml ( 1597 bytes, from 2019-01-07 09:52:31) +- state_2d.xml ( 51552 bytes, from 2019-01-07 09:52:31) +- state_3d.xml ( 83505 bytes, from 2019-08-19 14:46:17) +- state_blt.xml ( 14252 bytes, from 2019-08-19 14:35:07) +- state_vg.xml ( 5975 bytes, from 2019-01-07 09:52:31) Copyright (C) 2012-2019 by the following authors: - Wladimir J. van der Laan <[email protected]> @@ -81,23 +81,32 @@ DEALINGS IN THE SOFTWARE. #define RS_FORMAT_X8R8G8B8 0x00000005 #define RS_FORMAT_A8R8G8B8 0x00000006 #define RS_FORMAT_YUY2 0x00000007 -#define RS_FORMAT_A8 0x00000010 -#define RS_FORMAT_R16F 0x00000011 -#define RS_FORMAT_G16R16F 0x00000012 -#define RS_FORMAT_A16B16G16R16F 0x00000013 -#define RS_FORMAT_R32F 0x00000014 -#define RS_FORMAT_G32R32F 0x00000015 -#define RS_FORMAT_A2B10G10R10 0x00000016 -#define RS_FORMAT_R8I 0x00000017 -#define RS_FORMAT_G8R8I 0x00000018 -#define RS_FORMAT_A8B8G8R8I 0x00000019 -#define RS_FORMAT_R16I 0x0000001a -#define RS_FORMAT_G16R16I 0x0000001b -#define RS_FORMAT_A16B16G16R16I 0x0000001c -#define RS_FORMAT_B10G11R11F 0x0000001d -#define RS_FORMAT_A2B10G10R10UI 0x0000001e -#define RS_FORMAT_G8R8 0x0000001f -#define RS_FORMAT_R8 0x00000023 +#define RS_FORMAT_64BPP_CLEAR 0x00000015 +#define PE_FORMAT_X4R4G4B4 0x00000000 +#define PE_FORMAT_A4R4G4B4 0x00000001 +#define PE_FORMAT_X1R5G5B5 0x00000002 +#define PE_FORMAT_A1R5G5B5 0x00000003 +#define PE_FORMAT_R5G6B5 0x00000004 +#define PE_FORMAT_X8R8G8B8 0x00000005 +#define PE_FORMAT_A8R8G8B8 0x00000006 +#define PE_FORMAT_YUY2 0x00000007 +#define PE_FORMAT_A8 0x00000010 +#define PE_FORMAT_R16F 0x00000011 +#define PE_FORMAT_G16R16F 0x00000012 +#define PE_FORMAT_A16B16G16R16F 0x00000013 +#define PE_FORMAT_R32F 0x00000014 +#define PE_FORMAT_G32R32F 0x00000015 +#define PE_FORMAT_A2B10G10R10 0x00000016 +#define PE_FORMAT_R8I 0x00000017 +#define PE_FORMAT_G8R8I 0x00000018 +#define PE_FORMAT_A8B8G8R8I 0x00000019 +#define PE_FORMAT_R16I 0x0000001a +#define PE_FORMAT_G16R16I 0x0000001b +#define PE_FORMAT_A16B16G16R16I 0x0000001c +#define PE_FORMAT_B10G11R11F 0x0000001d +#define PE_FORMAT_A2B10G10R10UI 0x0000001e +#define PE_FORMAT_G8R8 0x0000001f +#define PE_FORMAT_R8 0x00000023 #define LOGIC_OP_CLEAR 0x00000000 #define LOGIC_OP_NOR 0x00000001 #define LOGIC_OP_AND_INVERTED 0x00000002 @@ -114,6 +123,13 @@ DEALINGS IN THE SOFTWARE. #define LOGIC_OP_OR_REVERSE 0x0000000d #define LOGIC_OP_OR 0x0000000e #define LOGIC_OP_SET 0x0000000f +#define COLOR_OUTPUT_MODE_NORMAL 0x00000000 +#define COLOR_OUTPUT_MODE_A2B10G10R10UI 0x00000001 +#define COLOR_OUTPUT_MODE_UIF32 0x00000002 +#define COLOR_OUTPUT_MODE_U8 0x00000003 +#define COLOR_OUTPUT_MODE_U16 0x00000004 +#define COLOR_OUTPUT_MODE_I8 0x00000005 +#define COLOR_OUTPUT_MODE_I16 0x00000006 #define VARYING_NUM_COMPONENTS_VAR0__MASK 0x00000007 #define VARYING_NUM_COMPONENTS_VAR0__SHIFT 0 #define VARYING_NUM_COMPONENTS_VAR0(x) (((x) << VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VARYING_NUM_COMPONENTS_VAR0__MASK) @@ -587,7 +603,13 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PS_CONTROL 0x00001010 #define VIVS_PS_CONTROL_BYPASS 0x00000001 -#define VIVS_PS_CONTROL_UNK1 0x00000002 +#define VIVS_PS_CONTROL_SATURATE_RT0 0x00000002 +#define VIVS_PS_CONTROL_SATURATE_RT1 0x00000004 +#define VIVS_PS_CONTROL_SATURATE_RT2 0x00000008 +#define VIVS_PS_CONTROL_SATURATE_RT3 0x00000010 +#define VIVS_PS_CONTROL_RT_COUNT__MASK 0x00000700 +#define VIVS_PS_CONTROL_RT_COUNT__SHIFT 8 +#define VIVS_PS_CONTROL_RT_COUNT(x) (((x) << VIVS_PS_CONTROL_RT_COUNT__SHIFT) & VIVS_PS_CONTROL_RT_COUNT__MASK) #define VIVS_PS_PERF_COUNTER 0x00001014 @@ -605,12 +627,37 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PS_INST_ADDR 0x00001028 -#define VIVS_PS_UNK0102C 0x0000102c +#define VIVS_PS_CONTROL2 0x0000102c +#define VIVS_PS_CONTROL2_SATURATE_RT4 0x00000080 +#define VIVS_PS_CONTROL2_SATURATE_RT5 0x00008000 +#define VIVS_PS_CONTROL2_SATURATE_RT6 0x00800000 +#define VIVS_PS_CONTROL2_SATURATE_RT7 0x80000000 #define VIVS_PS_CONTROL_EXT 0x00001030 -#define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__MASK 0x00000003 -#define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__SHIFT 0 -#define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT(x) (((x) << VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__SHIFT) & VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__MASK) +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__MASK 0x00000007 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__SHIFT 0 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__MASK) +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__MASK 0x00000070 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__SHIFT 4 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__MASK) +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__MASK 0x00000700 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__SHIFT 8 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__MASK) +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__MASK 0x00007000 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__SHIFT 12 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__MASK) +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__MASK 0x00070000 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__SHIFT 16 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__MASK) +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__MASK 0x00700000 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__SHIFT 20 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__MASK) +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__MASK 0x07000000 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__SHIFT 24 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__MASK) +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__MASK 0x70000000 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__SHIFT 28 +#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__MASK) #define VIVS_PS_UNK01034 0x00001034 @@ -1003,8 +1050,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PE_LOGIC_OP_UNK24__SHIFT 24 #define VIVS_PE_LOGIC_OP_UNK24(x) (((x) << VIVS_PE_LOGIC_OP_UNK24__SHIFT) & VIVS_PE_LOGIC_OP_UNK24__MASK) #define VIVS_PE_LOGIC_OP_UNK24_MASK 0x08000000 -#define VIVS_PE_LOGIC_OP_UNK31_MASK 0x40000000 -#define VIVS_PE_LOGIC_OP_UNK31 0x80000000 +#define VIVS_PE_LOGIC_OP_SRGB_MASK 0x40000000 +#define VIVS_PE_LOGIC_OP_SRGB 0x80000000 #define VIVS_PE_DITHER(i0) (0x000014a8 + 0x4*(i0)) #define VIVS_PE_DITHER__ESIZE 0x00000004 @@ -1064,13 +1111,19 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PE_RT_CONFIG_STRIDE__MASK 0x0000ffff #define VIVS_PE_RT_CONFIG_STRIDE__SHIFT 0 #define VIVS_PE_RT_CONFIG_STRIDE(x) (((x) << VIVS_PE_RT_CONFIG_STRIDE__SHIFT) & VIVS_PE_RT_CONFIG_STRIDE__MASK) -#define VIVS_PE_RT_CONFIG_UNK16__MASK 0xffff0000 -#define VIVS_PE_RT_CONFIG_UNK16__SHIFT 16 -#define VIVS_PE_RT_CONFIG_UNK16(x) (((x) << VIVS_PE_RT_CONFIG_UNK16__SHIFT) & VIVS_PE_RT_CONFIG_UNK16__MASK) +#define VIVS_PE_RT_CONFIG_FORMAT__MASK 0x001f0000 +#define VIVS_PE_RT_CONFIG_FORMAT__SHIFT 16 +#define VIVS_PE_RT_CONFIG_FORMAT(x) (((x) << VIVS_PE_RT_CONFIG_FORMAT__SHIFT) & VIVS_PE_RT_CONFIG_FORMAT__MASK) +#define VIVS_PE_RT_CONFIG_SUPER_TILED 0x04000000 +#define VIVS_PE_RT_CONFIG_UNK28 0x10000000 #define VIVS_PE_HALTI5_UNK14920(i0) (0x00014920 + 0x4*(i0)) #define VIVS_PE_HALTI5_UNK14920__ESIZE 0x00000004 #define VIVS_PE_HALTI5_UNK14920__LEN 0x00000007 +#define VIVS_PE_HALTI5_UNK14920_COMPONENTS__MASK 0x000000f0 +#define VIVS_PE_HALTI5_UNK14920_COMPONENTS__SHIFT 4 +#define VIVS_PE_HALTI5_UNK14920_COMPONENTS(x) (((x) << VIVS_PE_HALTI5_UNK14920_COMPONENTS__SHIFT) & VIVS_PE_HALTI5_UNK14920_COMPONENTS__MASK) +#define VIVS_PE_HALTI5_UNK14920_UNK8 0x00000100 #define VIVS_PE_HALTI5_UNK14940(i0) (0x00014940 + 0x4*(i0)) #define VIVS_PE_HALTI5_UNK14940__ESIZE 0x00000004 @@ -1607,9 +1660,10 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_SAMPLER_UNK10480(i0) (0x00010480 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_ASTC0(i0) (0x00010500 + 0x4*(i0)) -#define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK 0x000000ff +#define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK 0x0000000f #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT 0 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK) +#define VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB 0x00000010 #define VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK 0x0000ff00 #define VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT 8 #define VIVS_NTE_SAMPLER_ASTC0_UNK8(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK) @@ -1733,6 +1787,17 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK 0x00006000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT 13 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK) +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_ENABLE 0x00020000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__MASK 0x001c0000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__SHIFT 18 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_LE 0x00000000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_GE 0x00040000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_LT 0x00080000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_GT 0x000c0000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_EQ 0x00100000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_NE 0x00140000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_ALWAYS 0x00180000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_NEVER 0x001c0000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK21 0x00200000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK22 0x00400000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_RGB 0x00800000 |