diff options
| author | José Fonseca <[email protected]> | 2012-02-20 20:49:03 +0000 |
|---|---|---|
| committer | José Fonseca <[email protected]> | 2012-02-21 08:23:20 +0000 |
| commit | a206c4cd69a881bf3f8d960607d604b6d53e3a26 (patch) | |
| tree | e1e18c312b31b5615c30af316505a2f993cde919 /src/gallium/auxiliary/tgsi | |
| parent | d394bc5853f70f5a2d4c4b396e55b96c1ba63be7 (diff) | |
gallivm: Fix TGSI_OPCODE_ARR's translation.
Like TGSI_OPCODE_ARL, destination should be an integer.
This fixes invalid LLVM IR on an internal state tracker (currently Mesa
never emits this opcode).
In the future consider making ADDR register also a integer-as-float array,
like all other register kinds, or simply replace ADDR & ARR/ARL with
integer temp and instructions.
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/auxiliary/tgsi')
| -rw-r--r-- | src/gallium/auxiliary/tgsi/tgsi_info.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c index a44f48ca881..81df96b3c7a 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_info.c +++ b/src/gallium/auxiliary/tgsi/tgsi_info.c @@ -333,6 +333,7 @@ tgsi_opcode_infer_dst_type( uint opcode ) case TGSI_OPCODE_MOD: case TGSI_OPCODE_UARL: case TGSI_OPCODE_ARL: + case TGSI_OPCODE_ARR: case TGSI_OPCODE_IABS: case TGSI_OPCODE_ISSG: return TGSI_TYPE_SIGNED; |