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authorZack Rusin <[email protected]>2008-05-15 17:46:20 -0400
committerZack Rusin <[email protected]>2008-05-17 13:58:44 -0400
commit59766ac273c426557b7790b0fcb566c8095fd820 (patch)
treefb2e73a60a028e6c4bc9e6431eedc8733d66cd27 /src/gallium/auxiliary/gallivm/tgsitollvm.cpp
parent735752e8dceeec9b202147d1d19ef3dc70e08673 (diff)
llvm: implement sub and abs
Diffstat (limited to 'src/gallium/auxiliary/gallivm/tgsitollvm.cpp')
-rw-r--r--src/gallium/auxiliary/gallivm/tgsitollvm.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/auxiliary/gallivm/tgsitollvm.cpp b/src/gallium/auxiliary/gallivm/tgsitollvm.cpp
index ab8c851f148..5465d3a95ef 100644
--- a/src/gallium/auxiliary/gallivm/tgsitollvm.cpp
+++ b/src/gallium/auxiliary/gallivm/tgsitollvm.cpp
@@ -740,6 +740,7 @@ translate_instructionir(llvm::Module *module,
}
break;
case TGSI_OPCODE_SUB: {
+ out = instr->sub(inputs[0], inputs[1]);
}
break;
case TGSI_OPCODE_LERP: {
@@ -781,6 +782,7 @@ translate_instructionir(llvm::Module *module,
case TGSI_OPCODE_MULTIPLYMATRIX:
break;
case TGSI_OPCODE_ABS: {
+ out = instr->abs(inputs[0]);
}
break;
case TGSI_OPCODE_RCC: