diff options
| author | Jonathan Marek <[email protected]> | 2020-06-16 09:11:02 -0400 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-06-18 03:15:27 +0000 |
| commit | b6b98e95106b8d010d0d71baaba8637d5f6aaa3b (patch) | |
| tree | 8e70d607853bc7fc69ed4fbf68a6772b80fdeac5 /src/freedreno | |
| parent | ff2efd095e5a7543268e40112978b293a82518a7 (diff) | |
turnip: fix a sample shading case
Check pipeline's sampleShadingEnable to enable sample shading.
Also fix behavior of gl_Fragcoord with sample shading.
Fixes at least:
dEQP-VK.pipeline.multisample.min_sample_shading.min_0_5.samples_4.primitive_triangle
Signed-off-by: Jonathan Marek <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5499>
Diffstat (limited to 'src/freedreno')
| -rw-r--r-- | src/freedreno/vulkan/tu_pipeline.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index f48958321d3..7befceddc21 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -1173,7 +1173,7 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs) uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid; uint32_t smask_in_regid; - bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */ + bool sample_shading = fs->per_samp | fs->key.sample_shading; bool enable_varyings = fs->total_in > 0; samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID); @@ -1258,6 +1258,11 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs) A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) | COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE)); tu_cs_emit(cs, + /* these two bits (UNK4/UNK5) relate to fragcoord + * without them, fragcoord is the same for all samples + */ + COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK4) | + COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK5) | CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) | CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) | CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) | @@ -1876,6 +1881,10 @@ tu_pipeline_shader_key_init(struct ir3_shader_key *key, key->msaa = true; } + /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */ + if (msaa_info->sampleShadingEnable) + key->sample_shading = true; + /* TODO: Populate the remaining fields of ir3_shader_key. */ } |