freedreno/a6xx: Document the CP_SET_DRAW_STATE enable bits

There are bits for binning, gmem and sysmem.

Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Rob Clark <[email protected]>
Signed-off-by: Kristian H. Kristensen <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3131>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3131>

2 files changed, 21 insertions, 22 deletions

diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml
index f94e8e4e10b..3a7865b489d 100644
--- a/src/freedreno/registers/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno_pm4.xml
@@ -762,13 +762,9 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 			<bitfield name="DISABLE" pos="17" type="boolean"/>
 			<bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
 			<bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
-			<!--
-			I think this is a bitmask of states that this group applies to
-			(ie. binning/bypass/gmem)?  At least starting w/ a6xx blob
-			emits different VS state at the same time, with ENABLE_MASK=0x1
-			for binning pass VS state, and ENABLE_MASK=0x6 for full VS.
-			-->
-			<bitfield name="ENABLE_MASK" low="20" high="23" variants="A6XX-"/>
+			<bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/>
+			<bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/>
+			<bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/>
 			<bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
 		</reg32>
 		<reg32 offset="1" name="1">
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index 3d5a9835970..49ea11acfaa 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -2462,6 +2462,9 @@ struct tu_draw_info
    uint64_t count_buffer_offset;
 };
 
+#define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
+#define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
+
 enum tu_draw_state_group_id
 {
    TU_DRAW_STATE_PROGRAM,
@@ -3155,49 +3158,49 @@ tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_PROGRAM,
-            .enable_mask = 0x6,
+            .enable_mask = ENABLE_DRAW,
             .ib = pipeline->program.state_ib,
          };
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_PROGRAM_BINNING,
-            .enable_mask = 0x1,
+            .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
             .ib = pipeline->program.binning_state_ib,
          };
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_VI,
-            .enable_mask = 0x6,
+            .enable_mask = ENABLE_DRAW,
             .ib = pipeline->vi.state_ib,
          };
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_VI_BINNING,
-            .enable_mask = 0x1,
+            .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
             .ib = pipeline->vi.binning_state_ib,
          };
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_VP,
-            .enable_mask = 0x7,
+            .enable_mask = ENABLE_ALL,
             .ib = pipeline->vp.state_ib,
          };
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_RAST,
-            .enable_mask = 0x7,
+            .enable_mask = ENABLE_ALL,
             .ib = pipeline->rast.state_ib,
          };
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_DS,
-            .enable_mask = 0x7,
+            .enable_mask = ENABLE_ALL,
             .ib = pipeline->ds.state_ib,
          };
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_BLEND,
-            .enable_mask = 0x7,
+            .enable_mask = ENABLE_ALL,
             .ib = pipeline->blend.state_ib,
          };
    }
@@ -3207,13 +3210,13 @@ tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_VS_CONST,
-            .enable_mask = 0x7,
+            .enable_mask = ENABLE_ALL,
             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
          };
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_FS_CONST,
-            .enable_mask = 0x6,
+            .enable_mask = ENABLE_DRAW,
             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
          };
    }
@@ -3241,19 +3244,19 @@ tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_VS_TEX,
-            .enable_mask = 0x7,
+            .enable_mask = ENABLE_ALL,
             .ib = vs_tex,
          };
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_FS_TEX,
-            .enable_mask = 0x6,
+            .enable_mask = ENABLE_DRAW,
             .ib = fs_tex,
          };
       draw_state_groups[draw_state_group_count++] =
          (struct tu_draw_state_group) {
             .id = TU_DRAW_STATE_FS_IBO,
-            .enable_mask = 0x6,
+            .enable_mask = ENABLE_DRAW,
             .ib = fs_ibo,
          };
 
@@ -3267,10 +3270,10 @@ tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
    for (uint32_t i = 0; i < draw_state_group_count; i++) {
       const struct tu_draw_state_group *group = &draw_state_groups[i];
-
+      debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
       uint32_t cp_set_draw_state =
          CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
-         CP_SET_DRAW_STATE__0_ENABLE_MASK(group->enable_mask) |
+         group->enable_mask |
          CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
       uint64_t iova;
       if (group->ib.size) {