freedreno/perfcntrs: move to shared location

This should eventually be useful for VK_KHR_performance_query as well.
And in the more near term, for fdperf.

Attempt to not break android build is best-effort and untested.

Signed-off-by: Rob Clark <[email protected]>
Reviewed-by: Kristian H. Kristensen <[email protected]>

5 files changed, 2471 insertions, 0 deletions

diff --git a/src/freedreno/perfcntrs/fd2_perfcntr.c b/src/freedreno/perfcntrs/fd2_perfcntr.c
new file mode 100644
index 00000000000..06246f398eb
--- /dev/null
+++ b/src/freedreno/perfcntrs/fd2_perfcntr.c
@@ -0,0 +1,794 @@
+/*
+ * Copyright (C) 2018 Jonathan Marek <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Jonathan Marek <[email protected]>
+ *    Rob Clark <[email protected]>
+ */
+
+#include "util/u_half.h"
+#include "adreno_common.xml.h"
+#include "adreno_pm4.xml.h"
+#include "a2xx.xml.h"
+
+#define REG(_x) REG_A2XX_ ## _x
+#include "freedreno_perfcntr.h"
+
+static const struct fd_perfcntr_countable pa_su_countables[] = {
+	COUNTABLE(PERF_PAPC_PASX_REQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_FIRST_VECTOR, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_SECOND_VECTOR, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_FIRST_DEAD, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_SECOND_DEAD, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_VTX_KILL_DISCARD, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_VTX_NAN_DISCARD, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PA_INPUT_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PA_INPUT_NULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PA_INPUT_EVENT_FLAG, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PA_INPUT_END_OF_PACKET, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_VV_CULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_VV_CLIP_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_FAR, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_TOP, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLSM_NULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLSM_CLIP_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_INPUT_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_INPUT_CLIP_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_INPUT_NULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_POLYMODE_FACE_CULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_POLYMODE_BACK_CULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_POLYMODE_FRONT_CULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_POLYMODE_INVALID_FILL, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUTPUT_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUTPUT_NULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_REQ_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_REQ_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_REQ_STALLED, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_REC_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_REC_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_REC_STARVED_SX, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_REC_STALLED, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_REC_STALLED_POS_MEM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CCGSM_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CCGSM_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CCGSM_STALLED, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPRIM_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPRIM_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPRIM_STALLED, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLPRIM_STARVED_CCGSM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIPSM_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIPSM_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIPSM_WAIT_CLIPGA, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIPGA_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIPGA_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIPGA_STALLED, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIP_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_CLIP_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_STARVED_CLIP, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_STALLED_SC, UINT64, AVERAGE),
+	COUNTABLE(PERF_PAPC_SU_FACENESS_CULL, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_countable pa_sc_countables[] = {
+	COUNTABLE(SC_SR_WINDOW_VALID, UINT64, AVERAGE),
+	COUNTABLE(SC_CW_WINDOW_VALID, UINT64, AVERAGE),
+	COUNTABLE(SC_QM_WINDOW_VALID, UINT64, AVERAGE),
+	COUNTABLE(SC_FW_WINDOW_VALID, UINT64, AVERAGE),
+	COUNTABLE(SC_EZ_WINDOW_VALID, UINT64, AVERAGE),
+	COUNTABLE(SC_IT_WINDOW_VALID, UINT64, AVERAGE),
+	COUNTABLE(SC_STARVED_BY_PA, UINT64, AVERAGE),
+	COUNTABLE(SC_STALLED_BY_RB_TILE, UINT64, AVERAGE),
+	COUNTABLE(SC_STALLED_BY_RB_SAMP, UINT64, AVERAGE),
+	COUNTABLE(SC_STARVED_BY_RB_EZ, UINT64, AVERAGE),
+	COUNTABLE(SC_STALLED_BY_SAMPLE_FF, UINT64, AVERAGE),
+	COUNTABLE(SC_STALLED_BY_SQ, UINT64, AVERAGE),
+	COUNTABLE(SC_STALLED_BY_SP, UINT64, AVERAGE),
+	COUNTABLE(SC_TOTAL_NO_PRIMS, UINT64, AVERAGE),
+	COUNTABLE(SC_NON_EMPTY_PRIMS, UINT64, AVERAGE),
+	COUNTABLE(SC_NO_TILES_PASSING_QM, UINT64, AVERAGE),
+	COUNTABLE(SC_NO_PIXELS_PRE_EZ, UINT64, AVERAGE),
+	COUNTABLE(SC_NO_PIXELS_POST_EZ, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_countable vgt_countables[] = {
+	COUNTABLE(VGT_SQ_EVENT_WINDOW_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(VGT_SQ_SEND, UINT64, AVERAGE),
+	COUNTABLE(VGT_SQ_STALLED, UINT64, AVERAGE),
+	COUNTABLE(VGT_SQ_STARVED_BUSY, UINT64, AVERAGE),
+	COUNTABLE(VGT_SQ_STARVED_IDLE, UINT64, AVERAGE),
+	COUNTABLE(VGT_SQ_STATIC, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_EVENT_WINDOW_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_V_SEND, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_V_STALLED, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_V_STARVED_BUSY, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_V_STARVED_IDLE, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_V_STATIC, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_P_SEND, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_P_STALLED, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_P_STARVED_BUSY, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_P_STARVED_IDLE, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_P_STATIC, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_S_SEND, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_S_STALLED, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_S_STARVED_BUSY, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_S_STARVED_IDLE, UINT64, AVERAGE),
+	COUNTABLE(VGT_PA_CLIP_S_STATIC, UINT64, AVERAGE),
+	COUNTABLE(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(RBIU_IMMED_DATA_FIFO_STARVED, UINT64, AVERAGE),
+	COUNTABLE(RBIU_IMMED_DATA_FIFO_STALLED, UINT64, AVERAGE),
+	COUNTABLE(RBIU_DMA_REQUEST_FIFO_STARVED, UINT64, AVERAGE),
+	COUNTABLE(RBIU_DMA_REQUEST_FIFO_STALLED, UINT64, AVERAGE),
+	COUNTABLE(RBIU_DRAW_INITIATOR_FIFO_STARVED, UINT64, AVERAGE),
+	COUNTABLE(RBIU_DRAW_INITIATOR_FIFO_STALLED, UINT64, AVERAGE),
+	COUNTABLE(BIN_PRIM_NEAR_CULL, UINT64, AVERAGE),
+	COUNTABLE(BIN_PRIM_ZERO_CULL, UINT64, AVERAGE),
+	COUNTABLE(BIN_PRIM_FAR_CULL, UINT64, AVERAGE),
+	COUNTABLE(BIN_PRIM_BIN_CULL, UINT64, AVERAGE),
+	COUNTABLE(BIN_PRIM_FACE_CULL, UINT64, AVERAGE),
+	COUNTABLE(SPARE34, UINT64, AVERAGE),
+	COUNTABLE(SPARE35, UINT64, AVERAGE),
+	COUNTABLE(SPARE36, UINT64, AVERAGE),
+	COUNTABLE(SPARE37, UINT64, AVERAGE),
+	COUNTABLE(SPARE38, UINT64, AVERAGE),
+	COUNTABLE(SPARE39, UINT64, AVERAGE),
+	COUNTABLE(TE_SU_IN_VALID, UINT64, AVERAGE),
+	COUNTABLE(TE_SU_IN_READ, UINT64, AVERAGE),
+	COUNTABLE(TE_SU_IN_PRIM, UINT64, AVERAGE),
+	COUNTABLE(TE_SU_IN_EOP, UINT64, AVERAGE),
+	COUNTABLE(TE_SU_IN_NULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(TE_WK_IN_VALID, UINT64, AVERAGE),
+	COUNTABLE(TE_WK_IN_READ, UINT64, AVERAGE),
+	COUNTABLE(TE_OUT_PRIM_VALID, UINT64, AVERAGE),
+	COUNTABLE(TE_OUT_PRIM_READ, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_countable tcr_countables[] = {
+	COUNTABLE(DGMMPD_IPMUX0_STALL, UINT64, AVERAGE),
+	COUNTABLE(DGMMPD_IPMUX_ALL_STALL, UINT64, AVERAGE),
+	COUNTABLE(OPMUX0_L2_WRITES, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_countable tp0_countables[] = {
+	COUNTABLE(POINT_QUADS, UINT64, AVERAGE),
+	COUNTABLE(BILIN_QUADS, UINT64, AVERAGE),
+	COUNTABLE(ANISO_QUADS, UINT64, AVERAGE),
+	COUNTABLE(MIP_QUADS, UINT64, AVERAGE),
+	COUNTABLE(VOL_QUADS, UINT64, AVERAGE),
+	COUNTABLE(MIP_VOL_QUADS, UINT64, AVERAGE),
+	COUNTABLE(MIP_ANISO_QUADS, UINT64, AVERAGE),
+	COUNTABLE(VOL_ANISO_QUADS, UINT64, AVERAGE),
+	COUNTABLE(ANISO_2_1_QUADS, UINT64, AVERAGE),
+	COUNTABLE(ANISO_4_1_QUADS, UINT64, AVERAGE),
+	COUNTABLE(ANISO_6_1_QUADS, UINT64, AVERAGE),
+	COUNTABLE(ANISO_8_1_QUADS, UINT64, AVERAGE),
+	COUNTABLE(ANISO_10_1_QUADS, UINT64, AVERAGE),
+	COUNTABLE(ANISO_12_1_QUADS, UINT64, AVERAGE),
+	COUNTABLE(ANISO_14_1_QUADS, UINT64, AVERAGE),
+	COUNTABLE(ANISO_16_1_QUADS, UINT64, AVERAGE),
+	COUNTABLE(MIP_VOL_ANISO_QUADS, UINT64, AVERAGE),
+	COUNTABLE(ALIGN_2_QUADS, UINT64, AVERAGE),
+	COUNTABLE(ALIGN_4_QUADS, UINT64, AVERAGE),
+	COUNTABLE(PIX_0_QUAD, UINT64, AVERAGE),
+	COUNTABLE(PIX_1_QUAD, UINT64, AVERAGE),
+	COUNTABLE(PIX_2_QUAD, UINT64, AVERAGE),
+	COUNTABLE(PIX_3_QUAD, UINT64, AVERAGE),
+	COUNTABLE(PIX_4_QUAD, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD0, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD1, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD2, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD3, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD4, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD5, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD6, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD7, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD8, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD9, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD10, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD11, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD12, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD13, UINT64, AVERAGE),
+	COUNTABLE(TP_MIPMAP_LOD14, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_countable tcm_countables[] = {
+	COUNTABLE(QUAD0_RD_LAT_FIFO_EMPTY, UINT64, AVERAGE),
+	COUNTABLE(QUAD0_RD_LAT_FIFO_4TH_FULL, UINT64, AVERAGE),
+	COUNTABLE(QUAD0_RD_LAT_FIFO_HALF_FULL, UINT64, AVERAGE),
+	COUNTABLE(QUAD0_RD_LAT_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, UINT64, AVERAGE),
+	COUNTABLE(READ_STARVED_QUAD0, UINT64, AVERAGE),
+	COUNTABLE(READ_STARVED, UINT64, AVERAGE),
+	COUNTABLE(READ_STALLED_QUAD0, UINT64, AVERAGE),
+	COUNTABLE(READ_STALLED, UINT64, AVERAGE),
+	COUNTABLE(VALID_READ_QUAD0, UINT64, AVERAGE),
+	COUNTABLE(TC_TP_STARVED_QUAD0, UINT64, AVERAGE),
+	COUNTABLE(TC_TP_STARVED, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_countable tcf_countables[] = {
+	COUNTABLE(VALID_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(SINGLE_PHASES, UINT64, AVERAGE),
+	COUNTABLE(ANISO_PHASES, UINT64, AVERAGE),
+	COUNTABLE(MIP_PHASES, UINT64, AVERAGE),
+	COUNTABLE(VOL_PHASES, UINT64, AVERAGE),
+	COUNTABLE(MIP_VOL_PHASES, UINT64, AVERAGE),
+	COUNTABLE(MIP_ANISO_PHASES, UINT64, AVERAGE),
+	COUNTABLE(VOL_ANISO_PHASES, UINT64, AVERAGE),
+	COUNTABLE(ANISO_2_1_PHASES, UINT64, AVERAGE),
+	COUNTABLE(ANISO_4_1_PHASES, UINT64, AVERAGE),
+	COUNTABLE(ANISO_6_1_PHASES, UINT64, AVERAGE),
+	COUNTABLE(ANISO_8_1_PHASES, UINT64, AVERAGE),
+	COUNTABLE(ANISO_10_1_PHASES, UINT64, AVERAGE),
+	COUNTABLE(ANISO_12_1_PHASES, UINT64, AVERAGE),
+	COUNTABLE(ANISO_14_1_PHASES, UINT64, AVERAGE),
+	COUNTABLE(ANISO_16_1_PHASES, UINT64, AVERAGE),
+	COUNTABLE(MIP_VOL_ANISO_PHASES, UINT64, AVERAGE),
+	COUNTABLE(ALIGN_2_PHASES, UINT64, AVERAGE),
+	COUNTABLE(ALIGN_4_PHASES, UINT64, AVERAGE),
+	COUNTABLE(TPC_BUSY, UINT64, AVERAGE),
+	COUNTABLE(TPC_STALLED, UINT64, AVERAGE),
+	COUNTABLE(TPC_STARVED, UINT64, AVERAGE),
+	COUNTABLE(TPC_WORKING, UINT64, AVERAGE),
+	COUNTABLE(TPC_WALKER_BUSY, UINT64, AVERAGE),
+	COUNTABLE(TPC_WALKER_STALLED, UINT64, AVERAGE),
+	COUNTABLE(TPC_WALKER_WORKING, UINT64, AVERAGE),
+	COUNTABLE(TPC_ALIGNER_BUSY, UINT64, AVERAGE),
+	COUNTABLE(TPC_ALIGNER_STALLED, UINT64, AVERAGE),
+	COUNTABLE(TPC_ALIGNER_STALLED_BY_BLEND, UINT64, AVERAGE),
+	COUNTABLE(TPC_ALIGNER_STALLED_BY_CACHE, UINT64, AVERAGE),
+	COUNTABLE(TPC_ALIGNER_WORKING, UINT64, AVERAGE),
+	COUNTABLE(TPC_BLEND_BUSY, UINT64, AVERAGE),
+	COUNTABLE(TPC_BLEND_SYNC, UINT64, AVERAGE),
+	COUNTABLE(TPC_BLEND_STARVED, UINT64, AVERAGE),
+	COUNTABLE(TPC_BLEND_WORKING, UINT64, AVERAGE),
+	COUNTABLE(OPCODE_0x00, UINT64, AVERAGE),
+	COUNTABLE(OPCODE_0x01, UINT64, AVERAGE),
+	COUNTABLE(OPCODE_0x04, UINT64, AVERAGE),
+	COUNTABLE(OPCODE_0x10, UINT64, AVERAGE),
+	COUNTABLE(OPCODE_0x11, UINT64, AVERAGE),
+	COUNTABLE(OPCODE_0x12, UINT64, AVERAGE),
+	COUNTABLE(OPCODE_0x13, UINT64, AVERAGE),
+	COUNTABLE(OPCODE_0x18, UINT64, AVERAGE),
+	COUNTABLE(OPCODE_0x19, UINT64, AVERAGE),
+	COUNTABLE(OPCODE_0x1A, UINT64, AVERAGE),
+	COUNTABLE(OPCODE_OTHER, UINT64, AVERAGE),
+	COUNTABLE(IN_FIFO_0_EMPTY, UINT64, AVERAGE),
+	COUNTABLE(IN_FIFO_0_LT_HALF_FULL, UINT64, AVERAGE),
+	COUNTABLE(IN_FIFO_0_HALF_FULL, UINT64, AVERAGE),
+	COUNTABLE(IN_FIFO_0_FULL, UINT64, AVERAGE),
+	COUNTABLE(IN_FIFO_TPC_EMPTY, UINT64, AVERAGE),
+	COUNTABLE(IN_FIFO_TPC_LT_HALF_FULL, UINT64, AVERAGE),
+	COUNTABLE(IN_FIFO_TPC_HALF_FULL, UINT64, AVERAGE),
+	COUNTABLE(IN_FIFO_TPC_FULL, UINT64, AVERAGE),
+	COUNTABLE(TPC_TC_XFC, UINT64, AVERAGE),
+	COUNTABLE(TPC_TC_STATE, UINT64, AVERAGE),
+	COUNTABLE(TC_STALL, UINT64, AVERAGE),
+	COUNTABLE(QUAD0_TAPS, UINT64, AVERAGE),
+	COUNTABLE(QUADS, UINT64, AVERAGE),
+	COUNTABLE(TCA_SYNC_STALL, UINT64, AVERAGE),
+	COUNTABLE(TAG_STALL, UINT64, AVERAGE),
+	COUNTABLE(TCB_SYNC_STALL, UINT64, AVERAGE),
+	COUNTABLE(TCA_VALID, UINT64, AVERAGE),
+	COUNTABLE(PROBES_VALID, UINT64, AVERAGE),
+	COUNTABLE(MISS_STALL, UINT64, AVERAGE),
+	COUNTABLE(FETCH_FIFO_STALL, UINT64, AVERAGE),
+	COUNTABLE(TCO_STALL, UINT64, AVERAGE),
+	COUNTABLE(ANY_STALL, UINT64, AVERAGE),
+	COUNTABLE(TAG_MISSES, UINT64, AVERAGE),
+	COUNTABLE(TAG_HITS, UINT64, AVERAGE),
+	COUNTABLE(SUB_TAG_MISSES, UINT64, AVERAGE),
+	COUNTABLE(SET0_INVALIDATES, UINT64, AVERAGE),
+	COUNTABLE(SET1_INVALIDATES, UINT64, AVERAGE),
+	COUNTABLE(SET2_INVALIDATES, UINT64, AVERAGE),
+	COUNTABLE(SET3_INVALIDATES, UINT64, AVERAGE),
+	COUNTABLE(SET0_TAG_MISSES, UINT64, AVERAGE),
+	COUNTABLE(SET1_TAG_MISSES, UINT64, AVERAGE),
+	COUNTABLE(SET2_TAG_MISSES, UINT64, AVERAGE),
+	COUNTABLE(SET3_TAG_MISSES, UINT64, AVERAGE),
+	COUNTABLE(SET0_TAG_HITS, UINT64, AVERAGE),
+	COUNTABLE(SET1_TAG_HITS, UINT64, AVERAGE),
+	COUNTABLE(SET2_TAG_HITS, UINT64, AVERAGE),
+	COUNTABLE(SET3_TAG_HITS, UINT64, AVERAGE),
+	COUNTABLE(SET0_SUB_TAG_MISSES, UINT64, AVERAGE),
+	COUNTABLE(SET1_SUB_TAG_MISSES, UINT64, AVERAGE),
+	COUNTABLE(SET2_SUB_TAG_MISSES, UINT64, AVERAGE),
+	COUNTABLE(SET3_SUB_TAG_MISSES, UINT64, AVERAGE),
+	COUNTABLE(SET0_EVICT1, UINT64, AVERAGE),
+	COUNTABLE(SET0_EVICT2, UINT64, AVERAGE),
+	COUNTABLE(SET0_EVICT3, UINT64, AVERAGE),
+	COUNTABLE(SET0_EVICT4, UINT64, AVERAGE),
+	COUNTABLE(SET0_EVICT5, UINT64, AVERAGE),
+	COUNTABLE(SET0_EVICT6, UINT64, AVERAGE),
+	COUNTABLE(SET0_EVICT7, UINT64, AVERAGE),
+	COUNTABLE(SET0_EVICT8, UINT64, AVERAGE),
+	COUNTABLE(SET1_EVICT1, UINT64, AVERAGE),
+	COUNTABLE(SET1_EVICT2, UINT64, AVERAGE),
+	COUNTABLE(SET1_EVICT3, UINT64, AVERAGE),
+	COUNTABLE(SET1_EVICT4, UINT64, AVERAGE),
+	COUNTABLE(SET1_EVICT5, UINT64, AVERAGE),
+	COUNTABLE(SET1_EVICT6, UINT64, AVERAGE),
+	COUNTABLE(SET1_EVICT7, UINT64, AVERAGE),
+	COUNTABLE(SET1_EVICT8, UINT64, AVERAGE),
+	COUNTABLE(SET2_EVICT1, UINT64, AVERAGE),
+	COUNTABLE(SET2_EVICT2, UINT64, AVERAGE),
+	COUNTABLE(SET2_EVICT3, UINT64, AVERAGE),
+	COUNTABLE(SET2_EVICT4, UINT64, AVERAGE),
+	COUNTABLE(SET2_EVICT5, UINT64, AVERAGE),
+	COUNTABLE(SET2_EVICT6, UINT64, AVERAGE),
+	COUNTABLE(SET2_EVICT7, UINT64, AVERAGE),
+	COUNTABLE(SET2_EVICT8, UINT64, AVERAGE),
+	COUNTABLE(SET3_EVICT1, UINT64, AVERAGE),
+	COUNTABLE(SET3_EVICT2, UINT64, AVERAGE),
+	COUNTABLE(SET3_EVICT3, UINT64, AVERAGE),
+	COUNTABLE(SET3_EVICT4, UINT64, AVERAGE),
+	COUNTABLE(SET3_EVICT5, UINT64, AVERAGE),
+	COUNTABLE(SET3_EVICT6, UINT64, AVERAGE),
+	COUNTABLE(SET3_EVICT7, UINT64, AVERAGE),
+	COUNTABLE(SET3_EVICT8, UINT64, AVERAGE),
+	COUNTABLE(FF_EMPTY, UINT64, AVERAGE),
+	COUNTABLE(FF_LT_HALF_FULL, UINT64, AVERAGE),
+	COUNTABLE(FF_HALF_FULL, UINT64, AVERAGE),
+	COUNTABLE(FF_FULL, UINT64, AVERAGE),
+	COUNTABLE(FF_XFC, UINT64, AVERAGE),
+	COUNTABLE(FF_STALLED, UINT64, AVERAGE),
+	COUNTABLE(FG_MASKS, UINT64, AVERAGE),
+	COUNTABLE(FG_LEFT_MASKS, UINT64, AVERAGE),
+	COUNTABLE(FG_LEFT_MASK_STALLED, UINT64, AVERAGE),
+	COUNTABLE(FG_LEFT_NOT_DONE_STALL, UINT64, AVERAGE),
+	COUNTABLE(FG_LEFT_FG_STALL, UINT64, AVERAGE),
+	COUNTABLE(FG_LEFT_SECTORS, UINT64, AVERAGE),
+	COUNTABLE(FG0_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(FG0_STALLED, UINT64, AVERAGE),
+	COUNTABLE(MEM_REQ512, UINT64, AVERAGE),
+	COUNTABLE(MEM_REQ_SENT, UINT64, AVERAGE),
+	COUNTABLE(MEM_LOCAL_READ_REQ, UINT64, AVERAGE),
+	COUNTABLE(TC0_MH_STALLED, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_countable sq_countables[] = {
+	COUNTABLE(SQ_PIXEL_VECTORS_SUB, UINT64, AVERAGE),
+	COUNTABLE(SQ_VERTEX_VECTORS_SUB, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_ACTIVE_VTX_SIMD0, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_ACTIVE_VTX_SIMD0, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_ACTIVE_PIX_SIMD0, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_ACTIVE_PIX_SIMD0, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_ACTIVE_VTX_SIMD1, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_ACTIVE_VTX_SIMD1, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_ACTIVE_PIX_SIMD1, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_ACTIVE_PIX_SIMD1, UINT64, AVERAGE),
+	COUNTABLE(SQ_EXPORT_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU_CST_WRITTEN, UINT64, AVERAGE),
+	COUNTABLE(SQ_TEX_CST_WRITTEN, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU_CST_STALL, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU_TEX_STALL, UINT64, AVERAGE),
+	COUNTABLE(SQ_INST_WRITTEN, UINT64, AVERAGE),
+	COUNTABLE(SQ_BOOLEAN_WRITTEN, UINT64, AVERAGE),
+	COUNTABLE(SQ_LOOPS_WRITTEN, UINT64, AVERAGE),
+	COUNTABLE(SQ_PIXEL_SWAP_IN, UINT64, AVERAGE),
+	COUNTABLE(SQ_PIXEL_SWAP_OUT, UINT64, AVERAGE),
+	COUNTABLE(SQ_VERTEX_SWAP_IN, UINT64, AVERAGE),
+	COUNTABLE(SQ_VERTEX_SWAP_OUT, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU_VTX_INST_ISSUED, UINT64, AVERAGE),
+	COUNTABLE(SQ_TEX_VTX_INST_ISSUED, UINT64, AVERAGE),
+	COUNTABLE(SQ_VC_VTX_INST_ISSUED, UINT64, AVERAGE),
+	COUNTABLE(SQ_CF_VTX_INST_ISSUED, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU_PIX_INST_ISSUED, UINT64, AVERAGE),
+	COUNTABLE(SQ_TEX_PIX_INST_ISSUED, UINT64, AVERAGE),
+	COUNTABLE(SQ_VC_PIX_INST_ISSUED, UINT64, AVERAGE),
+	COUNTABLE(SQ_CF_PIX_INST_ISSUED, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_FIFO_EMPTY_SIMD0, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_FIFO_EMPTY_SIMD0, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_FIFO_EMPTY_SIMD1, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_FIFO_EMPTY_SIMD1, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU_NOPS, UINT64, AVERAGE),
+	COUNTABLE(SQ_PRED_SKIP, UINT64, AVERAGE),
+	COUNTABLE(SQ_SYNC_ALU_STALL_SIMD0_VTX, UINT64, AVERAGE),
+	COUNTABLE(SQ_SYNC_ALU_STALL_SIMD1_VTX, UINT64, AVERAGE),
+	COUNTABLE(SQ_SYNC_TEX_STALL_VTX, UINT64, AVERAGE),
+	COUNTABLE(SQ_SYNC_VC_STALL_VTX, UINT64, AVERAGE),
+	COUNTABLE(SQ_CONSTANTS_USED_SIMD0, UINT64, AVERAGE),
+	COUNTABLE(SQ_CONSTANTS_SENT_SP_SIMD0, UINT64, AVERAGE),
+	COUNTABLE(SQ_GPR_STALL_VTX, UINT64, AVERAGE),
+	COUNTABLE(SQ_GPR_STALL_PIX, UINT64, AVERAGE),
+	COUNTABLE(SQ_VTX_RS_STALL, UINT64, AVERAGE),
+	COUNTABLE(SQ_PIX_RS_STALL, UINT64, AVERAGE),
+	COUNTABLE(SQ_SX_PC_FULL, UINT64, AVERAGE),
+	COUNTABLE(SQ_SX_EXP_BUFF_FULL, UINT64, AVERAGE),
+	COUNTABLE(SQ_SX_POS_BUFF_FULL, UINT64, AVERAGE),
+	COUNTABLE(SQ_INTERP_QUADS, UINT64, AVERAGE),
+	COUNTABLE(SQ_INTERP_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(SQ_IN_PIXEL_STALL, UINT64, AVERAGE),
+	COUNTABLE(SQ_IN_VTX_STALL, UINT64, AVERAGE),
+	COUNTABLE(SQ_VTX_CNT, UINT64, AVERAGE),
+	COUNTABLE(SQ_VTX_VECTOR2, UINT64, AVERAGE),
+	COUNTABLE(SQ_VTX_VECTOR3, UINT64, AVERAGE),
+	COUNTABLE(SQ_VTX_VECTOR4, UINT64, AVERAGE),
+	COUNTABLE(SQ_PIXEL_VECTOR1, UINT64, AVERAGE),
+	COUNTABLE(SQ_PIXEL_VECTOR23, UINT64, AVERAGE),
+	COUNTABLE(SQ_PIXEL_VECTOR4, UINT64, AVERAGE),
+	COUNTABLE(SQ_CONSTANTS_USED_SIMD1, UINT64, AVERAGE),
+	COUNTABLE(SQ_CONSTANTS_SENT_SP_SIMD1, UINT64, AVERAGE),
+	COUNTABLE(SQ_SX_MEM_EXP_FULL, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_ACTIVE_VTX_SIMD2, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_ACTIVE_VTX_SIMD2, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_ACTIVE_PIX_SIMD2, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_ACTIVE_PIX_SIMD2, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_ACTIVE_VTX_SIMD3, UINT64, AVERAGE),
+	COUNTABLE(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_ACTIVE_PIX_SIMD3, UINT64, AVERAGE),
+	COUNTABLE(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_FIFO_EMPTY_SIMD2, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_FIFO_EMPTY_SIMD2, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_FIFO_EMPTY_SIMD3, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_FIFO_EMPTY_SIMD3, UINT64, AVERAGE),
+	COUNTABLE(SQ_SYNC_ALU_STALL_SIMD2_VTX, UINT64, AVERAGE),
+	COUNTABLE(SQ_PERFCOUNT_VTX_POP_THREAD, UINT64, AVERAGE),
+	COUNTABLE(SQ_SYNC_ALU_STALL_SIMD0_PIX, UINT64, AVERAGE),
+	COUNTABLE(SQ_SYNC_ALU_STALL_SIMD1_PIX, UINT64, AVERAGE),
+	COUNTABLE(SQ_SYNC_ALU_STALL_SIMD2_PIX, UINT64, AVERAGE),
+	COUNTABLE(SQ_PERFCOUNT_PIX_POP_THREAD, UINT64, AVERAGE),
+	COUNTABLE(SQ_SYNC_TEX_STALL_PIX, UINT64, AVERAGE),
+	COUNTABLE(SQ_SYNC_VC_STALL_PIX, UINT64, AVERAGE),
+	COUNTABLE(SQ_CONSTANTS_USED_SIMD2, UINT64, AVERAGE),
+	COUNTABLE(SQ_CONSTANTS_SENT_SP_SIMD2, UINT64, AVERAGE),
+	COUNTABLE(SQ_PERFCOUNT_VTX_DEALLOC_ACK, UINT64, AVERAGE),
+	COUNTABLE(SQ_PERFCOUNT_PIX_DEALLOC_ACK, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_FIFO_FULL_SIMD0, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_FIFO_FULL_SIMD0, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_FIFO_FULL_SIMD1, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_FIFO_FULL_SIMD1, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_FIFO_FULL_SIMD2, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_FIFO_FULL_SIMD2, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_FIFO_FULL_SIMD3, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_FIFO_FULL_SIMD3, UINT64, AVERAGE),
+	COUNTABLE(VC_PERF_STATIC, UINT64, AVERAGE),
+	COUNTABLE(VC_PERF_STALLED, UINT64, AVERAGE),
+	COUNTABLE(VC_PERF_STARVED, UINT64, AVERAGE),
+	COUNTABLE(VC_PERF_SEND, UINT64, AVERAGE),
+	COUNTABLE(VC_PERF_ACTUAL_STARVED, UINT64, AVERAGE),
+	COUNTABLE(PIXEL_THREAD_0_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(VERTEX_THREAD_0_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(PIXEL_THREAD_0_NUMBER, UINT64, AVERAGE),
+	COUNTABLE(VERTEX_THREAD_0_NUMBER, UINT64, AVERAGE),
+	COUNTABLE(VERTEX_EVENT_NUMBER, UINT64, AVERAGE),
+	COUNTABLE(PIXEL_EVENT_NUMBER, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_EF_PUSH, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_EF_POP_EVENT, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_EF_POP_NEW_VTX, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_EF_POP_DEALLOC, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_EF_POP_PVECTOR, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_EF_POP_PVECTOR_X, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_EF_POP_PVECTOR_VNZ, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_PB_DEALLOC, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_PI_STATE_PPB_POP, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_PI_RTR, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_PI_READ_EN, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_PI_BUFF_SWAP, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_SQ_FREE_BUFF, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_SQ_DEC, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_SC_VALID_CNTL_EVENT, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_SC_VALID_IJ_XFER, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_SC_NEW_VECTOR_1_Q, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_QUAL_NEW_VECTOR, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_QUAL_EVENT, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_END_BUFFER, UINT64, AVERAGE),
+	COUNTABLE(PTRBUFF_FILL_QUAD, UINT64, AVERAGE),
+	COUNTABLE(VERTS_WRITTEN_SPI, UINT64, AVERAGE),
+	COUNTABLE(TP_FETCH_INSTR_EXEC, UINT64, AVERAGE),
+	COUNTABLE(TP_FETCH_INSTR_REQ, UINT64, AVERAGE),
+	COUNTABLE(TP_DATA_RETURN, UINT64, AVERAGE),
+	COUNTABLE(SPI_WRITE_CYCLES_SP, UINT64, AVERAGE),
+	COUNTABLE(SPI_WRITES_SP, UINT64, AVERAGE),
+	COUNTABLE(SP_ALU_INSTR_EXEC, UINT64, AVERAGE),
+	COUNTABLE(SP_CONST_ADDR_TO_SQ, UINT64, AVERAGE),
+	COUNTABLE(SP_PRED_KILLS_TO_SQ, UINT64, AVERAGE),
+	COUNTABLE(SP_EXPORT_CYCLES_TO_SX, UINT64, AVERAGE),
+	COUNTABLE(SP_EXPORTS_TO_SX, UINT64, AVERAGE),
+	COUNTABLE(SQ_CYCLES_ELAPSED, UINT64, AVERAGE),
+	COUNTABLE(SQ_TCFS_OPT_ALLOC_EXEC, UINT64, AVERAGE),
+	COUNTABLE(SQ_TCFS_NO_OPT_ALLOC, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_NO_OPT_ALLOC, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_NO_OPT_ALLOC, UINT64, AVERAGE),
+	COUNTABLE(SQ_TCFS_ARB_XFC_CNT, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_ARB_XFC_CNT, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_ARB_XFC_CNT, UINT64, AVERAGE),
+	COUNTABLE(SQ_TCFS_CFS_UPDATE_CNT, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU0_CFS_UPDATE_CNT, UINT64, AVERAGE),
+	COUNTABLE(SQ_ALU1_CFS_UPDATE_CNT, UINT64, AVERAGE),
+	COUNTABLE(SQ_VTX_PUSH_THREAD_CNT, UINT64, AVERAGE),
+	COUNTABLE(SQ_VTX_POP_THREAD_CNT, UINT64, AVERAGE),
+	COUNTABLE(SQ_PIX_PUSH_THREAD_CNT, UINT64, AVERAGE),
+	COUNTABLE(SQ_PIX_POP_THREAD_CNT, UINT64, AVERAGE),
+	COUNTABLE(SQ_PIX_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(SQ_PIX_KILLED, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_countable sx_countables[] = {
+	COUNTABLE(SX_EXPORT_VECTORS, UINT64, AVERAGE),
+	COUNTABLE(SX_DUMMY_QUADS, UINT64, AVERAGE),
+	COUNTABLE(SX_ALPHA_FAIL, UINT64, AVERAGE),
+	COUNTABLE(SX_RB_QUAD_BUSY, UINT64, AVERAGE),
+	COUNTABLE(SX_RB_COLOR_BUSY, UINT64, AVERAGE),
+	COUNTABLE(SX_RB_QUAD_STALL, UINT64, AVERAGE),
+	COUNTABLE(SX_RB_COLOR_STALL, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_countable rb_countables[] = {
+	COUNTABLE(RBPERF_CNTX_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_CNTX_BUSY_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_SX_QUAD_STARVED, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_SX_QUAD_STARVED_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_GA_GC_CH0_SYS_REQ, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_GA_GC_CH0_SYS_REQ_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_GA_GC_CH1_SYS_REQ, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_GA_GC_CH1_SYS_REQ_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_MH_STARVED, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_MH_STARVED_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_AZ_BC_COLOR_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_AZ_BC_COLOR_BUSY_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_AZ_BC_Z_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_AZ_BC_Z_BUSY_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SC_TILE_RTR_N, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SC_TILE_RTR_N_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SC_SAMP_RTR_N, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SC_SAMP_RTR_N_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SX_QUAD_RTR_N, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SX_QUAD_RTR_N_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SX_COLOR_RTR_N, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SX_COLOR_RTR_N_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SC_SAMP_LZ_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ZXP_STALL, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ZXP_STALL_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_EVENT_PENDING, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_EVENT_PENDING_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_MH_VALID, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_MH_VALID_MAX, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_SX_RB_QUAD_SEND, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_SX_RB_COLOR_SEND, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_SC_RB_TILE_SEND, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_SC_RB_SAMPLE_SEND, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_SX_RB_MEM_EXPORT, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_SX_RB_QUAD_EVENT, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_SC_RB_TILE_EVENT_FILTERED, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_SC_RB_TILE_EVENT_ALL, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SC_EZ_SEND, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_SX_INDEX_SEND, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_GMEM_INTFO_RD, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_GMEM_INTF1_RD, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_GMEM_INTFO_WR, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_GMEM_INTF1_WR, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_CP_CONTEXT_DONE, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_RB_CP_CACHE_FLUSH, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ZPASS_DONE, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ZCMD_VALID, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_CCMD_VALID, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ACCUM_GRANT, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ACCUM_C0_GRANT, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ACCUM_C1_GRANT, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ACCUM_FULL_BE_WR, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ACCUM_REQUEST_NO_GRANT, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ACCUM_TIMEOUT_PULSE, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, UINT64, AVERAGE),
+	COUNTABLE(RBPERF_ACCUM_CAM_HIT_FLUSHING, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter pa_su_counters[] = {
+	COUNTER(PA_SU_PERFCOUNTER0_SELECT, PA_SU_PERFCOUNTER0_LOW, PA_SU_PERFCOUNTER0_HI),
+	COUNTER(PA_SU_PERFCOUNTER1_SELECT, PA_SU_PERFCOUNTER1_LOW, PA_SU_PERFCOUNTER1_HI),
+	COUNTER(PA_SU_PERFCOUNTER2_SELECT, PA_SU_PERFCOUNTER2_LOW, PA_SU_PERFCOUNTER2_HI),
+	COUNTER(PA_SU_PERFCOUNTER3_SELECT, PA_SU_PERFCOUNTER3_LOW, PA_SU_PERFCOUNTER3_HI),
+};
+
+static const struct fd_perfcntr_counter pa_sc_counters[] = {
+	COUNTER(PA_SC_PERFCOUNTER0_SELECT, PA_SC_PERFCOUNTER0_LOW, PA_SC_PERFCOUNTER0_HI),
+};
+
+static const struct fd_perfcntr_counter vgt_counters[] = {
+	COUNTER(VGT_PERFCOUNTER0_SELECT, VGT_PERFCOUNTER0_LOW, VGT_PERFCOUNTER0_HI),
+	COUNTER(VGT_PERFCOUNTER1_SELECT, VGT_PERFCOUNTER1_LOW, VGT_PERFCOUNTER1_HI),
+	COUNTER(VGT_PERFCOUNTER2_SELECT, VGT_PERFCOUNTER2_LOW, VGT_PERFCOUNTER2_HI),
+	COUNTER(VGT_PERFCOUNTER3_SELECT, VGT_PERFCOUNTER3_LOW, VGT_PERFCOUNTER3_HI),
+};
+
+static const struct fd_perfcntr_counter tcr_counters[] = {
+	COUNTER(TCR_PERFCOUNTER0_SELECT, TCR_PERFCOUNTER0_LOW, TCR_PERFCOUNTER0_HI),
+	COUNTER(TCR_PERFCOUNTER1_SELECT, TCR_PERFCOUNTER1_LOW, TCR_PERFCOUNTER1_HI),
+};
+
+static const struct fd_perfcntr_counter tp0_counters[] = {
+	COUNTER(TP0_PERFCOUNTER0_SELECT, TP0_PERFCOUNTER0_LOW, TP0_PERFCOUNTER0_HI),
+	COUNTER(TP0_PERFCOUNTER1_SELECT, TP0_PERFCOUNTER1_LOW, TP0_PERFCOUNTER1_HI),
+};
+
+static const struct fd_perfcntr_counter tcm_counters[] = {
+	COUNTER(TCM_PERFCOUNTER0_SELECT, TCM_PERFCOUNTER0_LOW, TCM_PERFCOUNTER0_HI),
+	COUNTER(TCM_PERFCOUNTER1_SELECT, TCM_PERFCOUNTER1_LOW, TCM_PERFCOUNTER1_HI),
+};
+
+static const struct fd_perfcntr_counter tcf_counters[] = {
+	COUNTER(TCF_PERFCOUNTER0_SELECT, TCF_PERFCOUNTER0_LOW, TCF_PERFCOUNTER0_HI),
+	COUNTER(TCF_PERFCOUNTER1_SELECT, TCF_PERFCOUNTER1_LOW, TCF_PERFCOUNTER1_HI),
+	COUNTER(TCF_PERFCOUNTER2_SELECT, TCF_PERFCOUNTER2_LOW, TCF_PERFCOUNTER2_HI),
+	COUNTER(TCF_PERFCOUNTER3_SELECT, TCF_PERFCOUNTER3_LOW, TCF_PERFCOUNTER3_HI),
+	COUNTER(TCF_PERFCOUNTER4_SELECT, TCF_PERFCOUNTER4_LOW, TCF_PERFCOUNTER4_HI),
+	COUNTER(TCF_PERFCOUNTER5_SELECT, TCF_PERFCOUNTER5_LOW, TCF_PERFCOUNTER5_HI),
+	COUNTER(TCF_PERFCOUNTER6_SELECT, TCF_PERFCOUNTER6_LOW, TCF_PERFCOUNTER6_HI),
+	COUNTER(TCF_PERFCOUNTER7_SELECT, TCF_PERFCOUNTER7_LOW, TCF_PERFCOUNTER7_HI),
+	COUNTER(TCF_PERFCOUNTER8_SELECT, TCF_PERFCOUNTER8_LOW, TCF_PERFCOUNTER8_HI),
+	COUNTER(TCF_PERFCOUNTER9_SELECT, TCF_PERFCOUNTER9_LOW, TCF_PERFCOUNTER9_HI),
+	COUNTER(TCF_PERFCOUNTER10_SELECT, TCF_PERFCOUNTER10_LOW, TCF_PERFCOUNTER10_HI),
+	COUNTER(TCF_PERFCOUNTER11_SELECT, TCF_PERFCOUNTER11_LOW, TCF_PERFCOUNTER11_HI),
+};
+
+static const struct fd_perfcntr_counter sq_counters[] = {
+	COUNTER(SQ_PERFCOUNTER0_SELECT, SQ_PERFCOUNTER0_LOW, SQ_PERFCOUNTER0_HI),
+	COUNTER(SQ_PERFCOUNTER1_SELECT, SQ_PERFCOUNTER1_LOW, SQ_PERFCOUNTER1_HI),
+	COUNTER(SQ_PERFCOUNTER2_SELECT, SQ_PERFCOUNTER2_LOW, SQ_PERFCOUNTER2_HI),
+	COUNTER(SQ_PERFCOUNTER3_SELECT, SQ_PERFCOUNTER3_LOW, SQ_PERFCOUNTER3_HI),
+};
+
+static const struct fd_perfcntr_countable rbbm_countables[] = {
+	COUNTABLE(RBBM1_COUNT, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_NRT_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_RB_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_SQ_CNTX0_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_SQ_CNTX17_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_VGT_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_VGT_NODMA_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_PA_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_SC_CNTX_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_TPC_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_TC_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_SX_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_CP_COHER_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_CP_NRT_BUSY, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_GFX_IDLE_STALL, UINT64, AVERAGE),
+	COUNTABLE(RBBM1_INTERRUPT, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_countable cp_countables[] = {
+	COUNTABLE(ALWAYS_COUNT, UINT64, AVERAGE),
+	COUNTABLE(TRANS_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(TRANS_FIFO_AF, UINT64, AVERAGE),
+	COUNTABLE(RCIU_PFPTRANS_WAIT, UINT64, AVERAGE),
+	COUNTABLE(RCIU_NRTTRANS_WAIT, UINT64, AVERAGE),
+	COUNTABLE(CSF_NRT_READ_WAIT, UINT64, AVERAGE),
+	COUNTABLE(CSF_I1_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(CSF_I2_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(CSF_ST_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(CSF_RING_ROQ_FULL, UINT64, AVERAGE),
+	COUNTABLE(CSF_I1_ROQ_FULL, UINT64, AVERAGE),
+	COUNTABLE(CSF_I2_ROQ_FULL, UINT64, AVERAGE),
+	COUNTABLE(CSF_ST_ROQ_FULL, UINT64, AVERAGE),
+	COUNTABLE(MIU_TAG_MEM_FULL, UINT64, AVERAGE),
+	COUNTABLE(MIU_WRITECLEAN, UINT64, AVERAGE),
+	COUNTABLE(MIU_NRT_WRITE_STALLED, UINT64, AVERAGE),
+	COUNTABLE(MIU_NRT_READ_STALLED, UINT64, AVERAGE),
+	COUNTABLE(ME_WRITE_CONFIRM_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(ME_VS_DEALLOC_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(ME_PS_DEALLOC_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(ME_REGS_VS_EVENT_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(ME_REGS_PS_EVENT_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(ME_REGS_CF_EVENT_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(ME_MICRO_RB_STARVED, UINT64, AVERAGE),
+	COUNTABLE(ME_MICRO_I1_STARVED, UINT64, AVERAGE),
+	COUNTABLE(ME_MICRO_I2_STARVED, UINT64, AVERAGE),
+	COUNTABLE(ME_MICRO_ST_STARVED, UINT64, AVERAGE),
+	COUNTABLE(RCIU_RBBM_DWORD_SENT, UINT64, AVERAGE),
+	COUNTABLE(ME_BUSY_CLOCKS, UINT64, AVERAGE),
+	COUNTABLE(ME_WAIT_CONTEXT_AVAIL, UINT64, AVERAGE),
+	COUNTABLE(PFP_TYPE0_PACKET, UINT64, AVERAGE),
+	COUNTABLE(PFP_TYPE3_PACKET, UINT64, AVERAGE),
+	COUNTABLE(CSF_RB_WPTR_NEQ_RPTR, UINT64, AVERAGE),
+	COUNTABLE(CSF_I1_SIZE_NEQ_ZERO, UINT64, AVERAGE),
+	COUNTABLE(CSF_I2_SIZE_NEQ_ZERO, UINT64, AVERAGE),
+	COUNTABLE(CSF_RBI1I2_FETCHING, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter sx_counters[] = {
+	COUNTER(SX_PERFCOUNTER0_SELECT, SX_PERFCOUNTER0_LOW, SX_PERFCOUNTER0_HI),
+};
+
+// We don't have the enums for MH perfcntrs
+#if 0
+static const struct fd_perfcntr_counter mh_counters[] = {
+	COUNTER(MH_PERFCOUNTER0_SELECT, MH_PERFCOUNTER0_LOW, MH_PERFCOUNTER0_HI),
+	COUNTER(MH_PERFCOUNTER1_SELECT, MH_PERFCOUNTER1_LOW, MH_PERFCOUNTER1_HI),
+};
+#endif
+
+static const struct fd_perfcntr_counter rbbm_counters[] = {
+	COUNTER(RBBM_PERFCOUNTER1_SELECT, RBBM_PERFCOUNTER1_LO, RBBM_PERFCOUNTER1_HI),
+};
+
+static const struct fd_perfcntr_counter cp_counters[] = {
+	COUNTER(CP_PERFCOUNTER_SELECT, CP_PERFCOUNTER_LO, CP_PERFCOUNTER_HI),
+};
+
+static const struct fd_perfcntr_counter rb_counters[] = {
+	COUNTER(RB_PERFCOUNTER0_SELECT, RB_PERFCOUNTER0_LOW, RB_PERFCOUNTER0_HI),
+};
+
+const struct fd_perfcntr_group a2xx_perfcntr_groups[] = {
+	GROUP("PA_SU", pa_su_counters, pa_su_countables),
+	GROUP("PA_SC", pa_sc_counters, pa_sc_countables),
+	GROUP("VGT", vgt_counters, vgt_countables),
+	GROUP("TCR", tcr_counters, tcr_countables),
+	GROUP("TP0", tp0_counters, tp0_countables),
+	GROUP("TCM", tcm_counters, tcm_countables),
+	GROUP("TCF", tcf_counters, tcf_countables),
+	GROUP("SQ", sq_counters, sq_countables),
+	GROUP("SX", sx_counters, sx_countables),
+//	GROUP("MH", mh_counters, mh_countables),
+	GROUP("RBBM", rbbm_counters, rbbm_countables),
+	GROUP("CP", cp_counters, cp_countables),
+	GROUP("RB", rb_counters, rb_countables),
+};
+
+const unsigned a2xx_num_perfcntr_groups = ARRAY_SIZE(a2xx_perfcntr_groups);
diff --git a/src/freedreno/perfcntrs/fd5_perfcntr.c b/src/freedreno/perfcntrs/fd5_perfcntr.c
new file mode 100644
index 00000000000..2d0579ca363
--- /dev/null
+++ b/src/freedreno/perfcntrs/fd5_perfcntr.c
@@ -0,0 +1,739 @@
+/*
+ * Copyright (C) 2018 Rob Clark <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <[email protected]>
+ */
+
+#ifndef FD5_PERFCNTR_H_
+#define FD5_PERFCNTR_H_
+
+#include "util/u_half.h"
+#include "adreno_common.xml.h"
+#include "a5xx.xml.h"
+
+#define REG(_x) REG_A5XX_ ## _x
+#include "freedreno_perfcntr.h"
+
+static const struct fd_perfcntr_counter cp_counters[] = {
+//RESERVED: for kernel
+//	COUNTER(CP_PERFCTR_CP_SEL_0, RBBM_PERFCTR_CP_0_LO, RBBM_PERFCTR_CP_0_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_1, RBBM_PERFCTR_CP_1_LO, RBBM_PERFCTR_CP_1_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_2, RBBM_PERFCTR_CP_2_LO, RBBM_PERFCTR_CP_2_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_3, RBBM_PERFCTR_CP_3_LO, RBBM_PERFCTR_CP_3_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_4, RBBM_PERFCTR_CP_4_LO, RBBM_PERFCTR_CP_4_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_5, RBBM_PERFCTR_CP_5_LO, RBBM_PERFCTR_CP_5_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_6, RBBM_PERFCTR_CP_6_LO, RBBM_PERFCTR_CP_6_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_7, RBBM_PERFCTR_CP_7_LO, RBBM_PERFCTR_CP_7_HI),
+};
+
+static const struct fd_perfcntr_countable cp_countables[] = {
+	COUNTABLE(PERF_CP_ALWAYS_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_BUSY_GFX_CORE_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PFP_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PFP_BUSY_WORKING, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PFP_STALL_CYCLES_ANY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PFP_STARVE_CYCLES_ANY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PFP_ICACHE_MISS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PFP_ICACHE_HIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PFP_MATCH_PM4_PKT_PROFILE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ME_BUSY_WORKING, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ME_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ME_STARVE_CYCLES_ANY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ME_FIFO_EMPTY_PFP_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ME_FIFO_EMPTY_PFP_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ME_FIFO_FULL_ME_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ME_FIFO_FULL_ME_NON_WORKING, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ME_STALL_CYCLES_ANY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ME_ICACHE_MISS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ME_ICACHE_HIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_NUM_PREEMPTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PREEMPTION_REACTION_DELAY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PREEMPTION_SWITCH_OUT_TIME, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PREEMPTION_SWITCH_IN_TIME, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_DEAD_DRAWS_IN_BIN_RENDER, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PREDICATED_DRAWS_KILLED, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_MODE_SWITCH, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ZPASS_DONE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_CONTEXT_DONE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_CACHE_FLUSH, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_LONG_PREEMPTIONS, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter ccu_counters[] = {
+	COUNTER(RB_PERFCTR_CCU_SEL_0, RBBM_PERFCTR_CCU_0_LO, RBBM_PERFCTR_CCU_0_HI),
+	COUNTER(RB_PERFCTR_CCU_SEL_1, RBBM_PERFCTR_CCU_1_LO, RBBM_PERFCTR_CCU_1_HI),
+	COUNTER(RB_PERFCTR_CCU_SEL_2, RBBM_PERFCTR_CCU_2_LO, RBBM_PERFCTR_CCU_2_HI),
+	COUNTER(RB_PERFCTR_CCU_SEL_3, RBBM_PERFCTR_CCU_3_LO, RBBM_PERFCTR_CCU_3_HI),
+};
+
+static const struct fd_perfcntr_countable ccu_countables[] = {
+	COUNTABLE(PERF_CCU_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_STARVE_CYCLES_FLAG_RETURN, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_BLOCKS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_BLOCKS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_BLOCK_HIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_BLOCK_HIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_PARTIAL_BLOCK_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_GMEM_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_GMEM_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG0_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG1_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG2_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG3_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG4_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG0_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG1_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG2_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG3_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG4_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_2D_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_2D_RD_REQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_2D_WR_REQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_2D_REORDER_STARVE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_2D_PIXELS, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter tse_counters[] = {
+	COUNTER(GRAS_PERFCTR_TSE_SEL_0, RBBM_PERFCTR_TSE_0_LO, RBBM_PERFCTR_TSE_0_HI),
+	COUNTER(GRAS_PERFCTR_TSE_SEL_1, RBBM_PERFCTR_TSE_1_LO, RBBM_PERFCTR_TSE_1_HI),
+	COUNTER(GRAS_PERFCTR_TSE_SEL_2, RBBM_PERFCTR_TSE_2_LO, RBBM_PERFCTR_TSE_2_HI),
+	COUNTER(GRAS_PERFCTR_TSE_SEL_3, RBBM_PERFCTR_TSE_3_LO, RBBM_PERFCTR_TSE_3_HI),
+};
+
+static const struct fd_perfcntr_countable tse_countables[] = {
+	COUNTABLE(PERF_TSE_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_CLIPPING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_STALL_CYCLES_RAS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_ZPLANE, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_STARVE_CYCLES_PC, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_INPUT_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_INPUT_NULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_TRIVAL_REJ_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_CLIPPED_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_ZERO_AREA_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_FACENESS_CULLED_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_ZERO_PIXEL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_OUTPUT_NULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_OUTPUT_VISIBLE_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_CINVOCATION, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_CPRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_2D_INPUT_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_2D_ALIVE_CLCLES, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter ras_counters[] = {
+	COUNTER(GRAS_PERFCTR_RAS_SEL_0, RBBM_PERFCTR_RAS_0_LO, RBBM_PERFCTR_RAS_0_HI),
+	COUNTER(GRAS_PERFCTR_RAS_SEL_1, RBBM_PERFCTR_RAS_1_LO, RBBM_PERFCTR_RAS_1_HI),
+	COUNTER(GRAS_PERFCTR_RAS_SEL_2, RBBM_PERFCTR_RAS_2_LO, RBBM_PERFCTR_RAS_2_HI),
+	COUNTER(GRAS_PERFCTR_RAS_SEL_3, RBBM_PERFCTR_RAS_3_LO, RBBM_PERFCTR_RAS_3_HI),
+};
+
+static const struct fd_perfcntr_countable ras_countables[] = {
+	COUNTABLE(PERF_RAS_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_SUPERTILE_ACTIVE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_STALL_CYCLES_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_STARVE_CYCLES_TSE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_SUPER_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_8X4_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_MASKGEN_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_FULLY_COVERED_SUPER_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_FULLY_COVERED_8X4_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_PRIM_KILLED_INVISILBE, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter lrz_counters[] = {
+	COUNTER(GRAS_PERFCTR_LRZ_SEL_0, RBBM_PERFCTR_LRZ_0_LO, RBBM_PERFCTR_LRZ_0_HI),
+	COUNTER(GRAS_PERFCTR_LRZ_SEL_1, RBBM_PERFCTR_LRZ_1_LO, RBBM_PERFCTR_LRZ_1_HI),
+	COUNTER(GRAS_PERFCTR_LRZ_SEL_2, RBBM_PERFCTR_LRZ_2_LO, RBBM_PERFCTR_LRZ_2_HI),
+	COUNTER(GRAS_PERFCTR_LRZ_SEL_3, RBBM_PERFCTR_LRZ_3_LO, RBBM_PERFCTR_LRZ_3_HI),
+};
+
+static const struct fd_perfcntr_countable lrz_countables[] = {
+	COUNTABLE(PERF_LRZ_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STARVE_CYCLES_RAS, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_RB, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_VSC, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_VPC, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_LRZ_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_LRZ_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_READ_LATENCY, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_MERGE_CACHE_UPDATING, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_MASKGEN, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_FULL_8X8_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_PARTIAL_8X8_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_TILE_KILLED, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_TOTAL_PIXEL, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter hlsq_counters[] = {
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_0, RBBM_PERFCTR_HLSQ_0_LO, RBBM_PERFCTR_HLSQ_0_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_1, RBBM_PERFCTR_HLSQ_1_LO, RBBM_PERFCTR_HLSQ_1_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_2, RBBM_PERFCTR_HLSQ_2_LO, RBBM_PERFCTR_HLSQ_2_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_3, RBBM_PERFCTR_HLSQ_3_LO, RBBM_PERFCTR_HLSQ_3_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_4, RBBM_PERFCTR_HLSQ_4_LO, RBBM_PERFCTR_HLSQ_4_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_5, RBBM_PERFCTR_HLSQ_5_LO, RBBM_PERFCTR_HLSQ_5_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_6, RBBM_PERFCTR_HLSQ_6_LO, RBBM_PERFCTR_HLSQ_6_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_7, RBBM_PERFCTR_HLSQ_7_LO, RBBM_PERFCTR_HLSQ_7_HI),
+};
+
+static const struct fd_perfcntr_countable hlsq_countables[] = {
+	COUNTABLE(PERF_HLSQ_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_STATE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_UCHE_LATENCY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_UCHE_LATENCY_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_FS_STAGE_32_WAVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_FS_STAGE_64_WAVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_QUADS, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_CS_INVOCATIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_COMPUTE_DRAWCALLS, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter pc_counters[] = {
+	COUNTER(PC_PERFCTR_PC_SEL_0, RBBM_PERFCTR_PC_0_LO, RBBM_PERFCTR_PC_0_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_1, RBBM_PERFCTR_PC_1_LO, RBBM_PERFCTR_PC_1_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_2, RBBM_PERFCTR_PC_2_LO, RBBM_PERFCTR_PC_2_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_3, RBBM_PERFCTR_PC_3_LO, RBBM_PERFCTR_PC_3_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_4, RBBM_PERFCTR_PC_4_LO, RBBM_PERFCTR_PC_4_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_5, RBBM_PERFCTR_PC_5_LO, RBBM_PERFCTR_PC_5_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_6, RBBM_PERFCTR_PC_6_LO, RBBM_PERFCTR_PC_6_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_7, RBBM_PERFCTR_PC_7_LO, RBBM_PERFCTR_PC_7_HI),
+};
+
+static const struct fd_perfcntr_countable pc_countables[] = {
+	COUNTABLE(PERF_PC_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_VFD, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_TSE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_VPC, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_TESS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_TSE_ONLY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_VPC_ONLY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_PASS1_TF_STALL_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_INDEX, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_POSITION, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STARVE_CYCLES_DI, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_VIS_STREAMS_LOADED, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_INSTANCES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_VPC_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_DEAD_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_LIVE_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_VERTEX_HITS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_IA_VERTICES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_IA_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_GS_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_HS_INVOCATIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_DS_INVOCATIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_VS_INVOCATIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_GS_INVOCATIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_DS_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_VPC_POS_DATA_TRANSACTION, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_3D_DRAWCALLS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_2D_DRAWCALLS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TESS_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TESS_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TESS_STALL_CYCLES_PC, UINT64, AVERAGE),
+	COUNTABLE(PERF_TESS_STARVE_CYCLES_PC, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter rb_counters[] = {
+	COUNTER(RB_PERFCTR_RB_SEL_0, RBBM_PERFCTR_RB_0_LO, RBBM_PERFCTR_RB_0_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_1, RBBM_PERFCTR_RB_1_LO, RBBM_PERFCTR_RB_1_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_2, RBBM_PERFCTR_RB_2_LO, RBBM_PERFCTR_RB_2_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_3, RBBM_PERFCTR_RB_3_LO, RBBM_PERFCTR_RB_3_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_4, RBBM_PERFCTR_RB_4_LO, RBBM_PERFCTR_RB_4_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_5, RBBM_PERFCTR_RB_5_LO, RBBM_PERFCTR_RB_5_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_6, RBBM_PERFCTR_RB_6_LO, RBBM_PERFCTR_RB_6_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_7, RBBM_PERFCTR_RB_7_LO, RBBM_PERFCTR_RB_7_HI),
+};
+
+static const struct fd_perfcntr_countable rb_countables[] = {
+	COUNTABLE(PERF_RB_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_CCU, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_HLSQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_FIFO0_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_FIFO1_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_FIFO2_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STARVE_CYCLES_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STARVE_CYCLES_LRZ_TILE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STARVE_CYCLES_CCU, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STARVE_CYCLES_Z_PLANE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STARVE_CYCLES_BARY_PLANE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_Z_WORKLOAD, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_HLSQ_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_Z_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_Z_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_C_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_C_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_TOTAL_PASS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_Z_PASS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_Z_FAIL, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_S_FAIL, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_BLENDED_FXP_COMPONENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_BLENDED_FP16_COMPONENTS, UINT64, AVERAGE),
+	COUNTABLE(RB_RESERVED, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_ALIVE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_STALL_CYCLES_A2D, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SRC, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_STARVE_CYCLES_DST, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_VALID_PIXELS, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter rbbm_counters[] = {
+//RESERVED: for kernel
+//	COUNTER(RBBM_PERFCTR_RBBM_SEL_0, RBBM_PERFCTR_RBBM_0_LO, RBBM_PERFCTR_RBBM_0_HI),
+	COUNTER(RBBM_PERFCTR_RBBM_SEL_1, RBBM_PERFCTR_RBBM_1_LO, RBBM_PERFCTR_RBBM_1_HI),
+	COUNTER(RBBM_PERFCTR_RBBM_SEL_2, RBBM_PERFCTR_RBBM_2_LO, RBBM_PERFCTR_RBBM_2_HI),
+	COUNTER(RBBM_PERFCTR_RBBM_SEL_3, RBBM_PERFCTR_RBBM_3_LO, RBBM_PERFCTR_RBBM_3_HI),
+};
+
+static const struct fd_perfcntr_countable rbbm_countables[] = {
+	COUNTABLE(PERF_RBBM_ALWAYS_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_ALWAYS_ON, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_TSE_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_RAS_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_PC_DCALL_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_PC_VSD_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_STATUS_MASKED, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_COM_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_DCOM_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_VBIF_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_VSC_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_TESS_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_UCHE_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_HLSQ_BUSY, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter sp_counters[] = {
+//RESERVED: for kernel
+//	COUNTER(SP_PERFCTR_SP_SEL_0,  RBBM_PERFCTR_SP_0_LO,  RBBM_PERFCTR_SP_0_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_1,  RBBM_PERFCTR_SP_1_LO,  RBBM_PERFCTR_SP_1_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_2,  RBBM_PERFCTR_SP_2_LO,  RBBM_PERFCTR_SP_2_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_3,  RBBM_PERFCTR_SP_3_LO,  RBBM_PERFCTR_SP_3_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_4,  RBBM_PERFCTR_SP_4_LO,  RBBM_PERFCTR_SP_4_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_5,  RBBM_PERFCTR_SP_5_LO,  RBBM_PERFCTR_SP_5_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_6,  RBBM_PERFCTR_SP_6_LO,  RBBM_PERFCTR_SP_6_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_7,  RBBM_PERFCTR_SP_7_LO,  RBBM_PERFCTR_SP_7_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_8,  RBBM_PERFCTR_SP_8_LO,  RBBM_PERFCTR_SP_8_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_9,  RBBM_PERFCTR_SP_9_LO,  RBBM_PERFCTR_SP_9_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_10, RBBM_PERFCTR_SP_10_LO, RBBM_PERFCTR_SP_10_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_11, RBBM_PERFCTR_SP_11_LO, RBBM_PERFCTR_SP_11_HI),
+};
+
+static const struct fd_perfcntr_countable sp_countables[] = {
+	COUNTABLE(PERF_SP_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ALU_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_EFU_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_STALL_CYCLES_VPC, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_STALL_CYCLES_TP, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_STALL_CYCLES_RB, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_SCHEDULER_NON_WORKING, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_CONTEXTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_CONTEXT_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_CTRL_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_LOAD_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_EMIT_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_NOP_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_WAIT_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_FETCH_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_IDLE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_END_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_LONG_SYNC_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_SHORT_SYNC_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_JOIN_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LM_ATOMICS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GM_ATOMICS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_BARY_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ADDR_LOCK_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_UCHE_READ_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_UCHE_WRITE_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_EXPORT_VPC_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_EXPORT_RB_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_PIXELS_KILLED, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ICL1_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ICL1_MISSES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ICL0_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ICL0_MISSES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_HS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_DS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_CS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GPR_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GPR_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LM_CH0_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LM_CH1_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LM_BANK_CONFLICTS, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter tp_counters[] = {
+	COUNTER(TPL1_PERFCTR_TP_SEL_0, RBBM_PERFCTR_TP_0_LO, RBBM_PERFCTR_TP_0_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_1, RBBM_PERFCTR_TP_1_LO, RBBM_PERFCTR_TP_1_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_2, RBBM_PERFCTR_TP_2_LO, RBBM_PERFCTR_TP_2_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_3, RBBM_PERFCTR_TP_3_LO, RBBM_PERFCTR_TP_3_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_4, RBBM_PERFCTR_TP_4_LO, RBBM_PERFCTR_TP_4_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_5, RBBM_PERFCTR_TP_5_LO, RBBM_PERFCTR_TP_5_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_6, RBBM_PERFCTR_TP_6_LO, RBBM_PERFCTR_TP_6_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_7, RBBM_PERFCTR_TP_7_LO, RBBM_PERFCTR_TP_7_HI),
+};
+
+static const struct fd_perfcntr_countable tp_countables[] = {
+	COUNTABLE(PERF_TP_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_LATENCY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_LATENCY_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_SAMPLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_LATENCY, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_CACHELINE_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_CACHELINE_MISSES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_SP_TP_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_TP_SP_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_RECEIVED, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_OFFSET, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_SHADOW, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_ARRAY, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_GRADIENT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_1D, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_2D, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_BUFFER, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_3D, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_CUBE, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_STATE_CACHE_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_STATE_CACHE_MISSES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_DIVERGENT_QUADS_RECEIVED, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_BINDLESS_STATE_CACHE_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_BINDLESS_STATE_CACHE_MISSES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_PRT_NON_RESIDENT_EVENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS_MIP, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS_ANISO, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS_ZERO_LOD, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FLAG_CACHE_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FLAG_CACHE_MISSES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_5_L2_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter uche_counters[] = {
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_0, RBBM_PERFCTR_UCHE_0_LO, RBBM_PERFCTR_UCHE_0_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_1, RBBM_PERFCTR_UCHE_1_LO, RBBM_PERFCTR_UCHE_1_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_2, RBBM_PERFCTR_UCHE_2_LO, RBBM_PERFCTR_UCHE_2_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_3, RBBM_PERFCTR_UCHE_3_LO, RBBM_PERFCTR_UCHE_3_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_4, RBBM_PERFCTR_UCHE_4_LO, RBBM_PERFCTR_UCHE_4_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_5, RBBM_PERFCTR_UCHE_5_LO, RBBM_PERFCTR_UCHE_5_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_6, RBBM_PERFCTR_UCHE_6_LO, RBBM_PERFCTR_UCHE_6_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_7, RBBM_PERFCTR_UCHE_7_LO, RBBM_PERFCTR_UCHE_7_HI),
+};
+
+static const struct fd_perfcntr_countable uche_countables[] = {
+	COUNTABLE(PERF_UCHE_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_STALL_CYCLES_VBIF, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_LATENCY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_LATENCY_SAMPLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_TP, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_VFD, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_HLSQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_READ_REQUESTS_TP, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_READ_REQUESTS_VFD, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_READ_REQUESTS_HLSQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_READ_REQUESTS_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_READ_REQUESTS_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_WRITE_REQUESTS_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_WRITE_REQUESTS_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VPC, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VSC, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_EVICTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ0, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ1, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ2, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ3, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ4, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ5, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ6, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ7, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH0, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH1, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_GMEM_READ_BEATS, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_FLAG_COUNT, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter vfd_counters[] = {
+	COUNTER(VFD_PERFCTR_VFD_SEL_0, RBBM_PERFCTR_VFD_0_LO, RBBM_PERFCTR_VFD_0_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_1, RBBM_PERFCTR_VFD_1_LO, RBBM_PERFCTR_VFD_1_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_2, RBBM_PERFCTR_VFD_2_LO, RBBM_PERFCTR_VFD_2_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_3, RBBM_PERFCTR_VFD_3_LO, RBBM_PERFCTR_VFD_3_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_4, RBBM_PERFCTR_VFD_4_LO, RBBM_PERFCTR_VFD_4_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_5, RBBM_PERFCTR_VFD_5_LO, RBBM_PERFCTR_VFD_5_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_6, RBBM_PERFCTR_VFD_6_LO, RBBM_PERFCTR_VFD_6_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_7, RBBM_PERFCTR_VFD_7_LO, RBBM_PERFCTR_VFD_7_HI),
+};
+
+static const struct fd_perfcntr_countable vfd_countables[] = {
+	COUNTABLE(PERF_VFD_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_VPC_ALLOC, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_MISS_VB, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_MISS_Q, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_SP_INFO, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_SP_ATTR, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_VFDP_VB, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_VFDP_Q, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_DECODER_PACKER_STALL, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STARVE_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_RBUFFER_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_ATTR_INFO_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_DECODED_ATTRIBUTE_BYTES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_NUM_ATTRIBUTES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_UPPER_SHADER_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_LOWER_SHADER_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_MODE_0_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_MODE_1_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_MODE_2_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_MODE_3_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_MODE_4_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_TOTAL_VERTICES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_NUM_ATTR_MISS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_1_BURST_REQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_INDEX, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_PROG, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFDP_STARVE_CYCLES_PC, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFDP_VS_STAGE_32_WAVES, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter vpc_counters[] = {
+	COUNTER(VPC_PERFCTR_VPC_SEL_0, RBBM_PERFCTR_VPC_0_LO, RBBM_PERFCTR_VPC_0_HI),
+	COUNTER(VPC_PERFCTR_VPC_SEL_1, RBBM_PERFCTR_VPC_1_LO, RBBM_PERFCTR_VPC_1_HI),
+	COUNTER(VPC_PERFCTR_VPC_SEL_2, RBBM_PERFCTR_VPC_2_LO, RBBM_PERFCTR_VPC_2_HI),
+	COUNTER(VPC_PERFCTR_VPC_SEL_3, RBBM_PERFCTR_VPC_3_LO, RBBM_PERFCTR_VPC_3_HI),
+};
+
+static const struct fd_perfcntr_countable vpc_countables[] = {
+	COUNTABLE(PERF_VPC_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STALL_CYCLES_VFD_WACK, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STALL_CYCLES_PC, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STALL_CYCLES_SP_LM, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_POS_EXPORT_STALL_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STARVE_CYCLES_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STARVE_CYCLES_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_PC_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_SP_COMPONENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_SP_LM_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_SP_LM_COMPONENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_SP_LM_DWORDS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STREAMOUT_COMPONENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_GRANT_PHASES, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter vsc_counters[] = {
+	COUNTER(VSC_PERFCTR_VSC_SEL_0, RBBM_PERFCTR_VSC_0_LO, RBBM_PERFCTR_VSC_0_HI),
+	COUNTER(VSC_PERFCTR_VSC_SEL_1, RBBM_PERFCTR_VSC_1_LO, RBBM_PERFCTR_VSC_1_HI),
+};
+
+static const struct fd_perfcntr_countable vsc_countables[] = {
+	COUNTABLE(PERF_VSC_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VSC_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VSC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_VSC_EOT_NUM, UINT64, AVERAGE),
+};
+
+/* VBIF counters probably not too userful for userspace, and they make
+ * frameretrace take many more passes to collect all the metrics, so
+ * for now let's hide them.
+ */
+#if 0
+/* VBIF counters break the pattern a bit, with enable and clear regs: */
+static const struct fd_perfcntr_counter vbif_counters[] = {
+	COUNTER2(VBIF_PERF_CNT_SEL0, VBIF_PERF_CNT_LOW0, VBIF_PERF_CNT_HIGH0, VBIF_PERF_CNT_EN0, VBIF_PERF_CNT_CLR0),
+	COUNTER2(VBIF_PERF_CNT_SEL1, VBIF_PERF_CNT_LOW1, VBIF_PERF_CNT_HIGH1, VBIF_PERF_CNT_EN1, VBIF_PERF_CNT_CLR1),
+	COUNTER2(VBIF_PERF_CNT_SEL2, VBIF_PERF_CNT_LOW2, VBIF_PERF_CNT_HIGH2, VBIF_PERF_CNT_EN2, VBIF_PERF_CNT_CLR2),
+	COUNTER2(VBIF_PERF_CNT_SEL3, VBIF_PERF_CNT_LOW3, VBIF_PERF_CNT_HIGH3, VBIF_PERF_CNT_EN3, VBIF_PERF_CNT_CLR3),
+};
+
+static const struct fd_perfcntr_countable vbif_countables[] = {
+	COUNTABLE(AXI_READ_REQUESTS_ID_0, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_1, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_2, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_3, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_4, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_5, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_6, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_7, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_8, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_9, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_10, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_11, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_12, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_13, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_14, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_ID_15, UINT64, AVERAGE),
+	COUNTABLE(AXI0_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI1_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI2_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI3_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_0, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_1, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_2, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_3, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_4, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_5, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_6, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_7, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_8, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_9, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_10, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_11, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_12, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_13, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_14, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_ID_15, UINT64, AVERAGE),
+	COUNTABLE(AXI0_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI1_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI2_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI3_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI_TOTAL_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_0, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_1, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_2, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_3, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_4, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_5, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_6, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_7, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_8, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_9, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_10, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_11, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_12, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_13, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_14, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_ID_15, UINT64, AVERAGE),
+	COUNTABLE(AXI0_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI1_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI2_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI3_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_0, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_1, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_2, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_3, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_4, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_5, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_6, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_7, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_8, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_9, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_10, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_11, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_12, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_13, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_14, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_ID_15, UINT64, AVERAGE),
+	COUNTABLE(AXI0_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI1_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI2_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI3_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
+	COUNTABLE(AXI_DATA_BEATS_TOTAL, UINT64, AVERAGE),
+};
+#endif
+
+const struct fd_perfcntr_group a5xx_perfcntr_groups[] = {
+	GROUP("CP", cp_counters, cp_countables),
+	GROUP("CCU", ccu_counters, ccu_countables),
+	GROUP("TSE", tse_counters, tse_countables),
+	GROUP("RAS", ras_counters, ras_countables),
+	GROUP("LRZ", lrz_counters, lrz_countables),
+	GROUP("HLSQ", hlsq_counters, hlsq_countables),
+	GROUP("PC", pc_counters, pc_countables),
+	GROUP("RB", rb_counters, rb_countables),
+	GROUP("RBBM", rbbm_counters, rbbm_countables),
+	GROUP("SP", sp_counters, sp_countables),
+	GROUP("TP", tp_counters, tp_countables),
+	GROUP("UCHE", uche_counters, uche_countables),
+	GROUP("VFD", vfd_counters, vfd_countables),
+	GROUP("VPC", vpc_counters, vpc_countables),
+	GROUP("VSC", vsc_counters, vsc_countables),
+//	GROUP("VBIF", vbif_counters, vbif_countables),
+};
+
+const unsigned a5xx_num_perfcntr_groups = ARRAY_SIZE(a5xx_perfcntr_groups);
+
+#endif /* FD5_PERFCNTR_H_ */
diff --git a/src/freedreno/perfcntrs/fd6_perfcntr.c b/src/freedreno/perfcntrs/fd6_perfcntr.c
new file mode 100644
index 00000000000..a3c62d1286f
--- /dev/null
+++ b/src/freedreno/perfcntrs/fd6_perfcntr.c
@@ -0,0 +1,778 @@
+/*
+ * Copyright (C) 2019 Rob Clark <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <[email protected]>
+ */
+
+#ifndef FD6_PERFCNTR_H_
+#define FD6_PERFCNTR_H_
+
+#include "util/u_half.h"
+#include "adreno_common.xml.h"
+#include "a6xx.xml.h"
+
+#define REG(_x) REG_A6XX_ ## _x
+#include "freedreno_perfcntr.h"
+
+static const struct fd_perfcntr_counter cp_counters[] = {
+//RESERVED: for kernel
+//	COUNTER(CP_PERFCTR_CP_SEL_0,  RBBM_PERFCTR_CP_0_LO,  RBBM_PERFCTR_CP_0_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_1,  RBBM_PERFCTR_CP_1_LO,  RBBM_PERFCTR_CP_1_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_2,  RBBM_PERFCTR_CP_2_LO,  RBBM_PERFCTR_CP_2_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_3,  RBBM_PERFCTR_CP_3_LO,  RBBM_PERFCTR_CP_3_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_4,  RBBM_PERFCTR_CP_4_LO,  RBBM_PERFCTR_CP_4_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_5,  RBBM_PERFCTR_CP_5_LO,  RBBM_PERFCTR_CP_5_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_6,  RBBM_PERFCTR_CP_6_LO,  RBBM_PERFCTR_CP_6_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_7,  RBBM_PERFCTR_CP_7_LO,  RBBM_PERFCTR_CP_7_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_8,  RBBM_PERFCTR_CP_8_LO,  RBBM_PERFCTR_CP_8_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_9,  RBBM_PERFCTR_CP_9_LO,  RBBM_PERFCTR_CP_9_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_10, RBBM_PERFCTR_CP_10_LO, RBBM_PERFCTR_CP_10_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_11, RBBM_PERFCTR_CP_11_LO, RBBM_PERFCTR_CP_11_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_12, RBBM_PERFCTR_CP_12_LO, RBBM_PERFCTR_CP_12_HI),
+	COUNTER(CP_PERFCTR_CP_SEL_13, RBBM_PERFCTR_CP_13_LO, RBBM_PERFCTR_CP_13_HI),
+};
+
+static const struct fd_perfcntr_countable cp_countables[] = {
+	COUNTABLE(PERF_CP_ALWAYS_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_BUSY_GFX_CORE_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_NUM_PREEMPTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PREEMPTION_REACTION_DELAY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PREEMPTION_SWITCH_OUT_TIME, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PREEMPTION_SWITCH_IN_TIME, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_DEAD_DRAWS_IN_BIN_RENDER, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PREDICATED_DRAWS_KILLED, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_MODE_SWITCH, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_ZPASS_DONE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_CONTEXT_DONE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_CACHE_FLUSH, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_LONG_PREEMPTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_I_CACHE_STARVE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_IDLE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_PM4_STARVE_RB_IB, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_PM4_STARVE_SDS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_MRB_STARVE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_RRB_STARVE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_VSD_STARVE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_VSD_DECODE_STARVE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_PIPE_OUT_STALL, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_SYNC_STALL, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_PM4_WFI_STALL, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_SYS_WFI_STALL, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_T4_EXEC, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_LOAD_STATE_EXEC, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_SAVE_SDS_STATE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_DRAW_EXEC, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_CTXT_REG_BUNCH_EXEC, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_EXEC_PROFILED, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_MEMORY_POOL_EMPTY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_MEMORY_POOL_SYNC_STALL, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_MEMORY_POOL_ABOVE_THRESH, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_AHB_WR_STALL_PRE_DRAWS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_AHB_STALL_SQE_GMU, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_AHB_STALL_SQE_WR_OTHER, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_AHB_STALL_SQE_RD_OTHER, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_CLUSTER0_EMPTY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_CLUSTER1_EMPTY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_CLUSTER2_EMPTY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_CLUSTER3_EMPTY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_CLUSTER4_EMPTY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_CLUSTER5_EMPTY, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PM4_DATA, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_PM4_HEADERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_VBIF_READ_BEATS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_VBIF_WRITE_BEATS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CP_SQE_INSTR_COUNTER, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter ccu_counters[] = {
+	COUNTER(RB_PERFCTR_CCU_SEL_0, RBBM_PERFCTR_CCU_0_LO, RBBM_PERFCTR_CCU_0_HI),
+	COUNTER(RB_PERFCTR_CCU_SEL_1, RBBM_PERFCTR_CCU_1_LO, RBBM_PERFCTR_CCU_1_HI),
+	COUNTER(RB_PERFCTR_CCU_SEL_2, RBBM_PERFCTR_CCU_2_LO, RBBM_PERFCTR_CCU_2_HI),
+	COUNTER(RB_PERFCTR_CCU_SEL_3, RBBM_PERFCTR_CCU_3_LO, RBBM_PERFCTR_CCU_3_HI),
+	COUNTER(RB_PERFCTR_CCU_SEL_4, RBBM_PERFCTR_CCU_4_LO, RBBM_PERFCTR_CCU_4_HI),
+};
+
+static const struct fd_perfcntr_countable ccu_countables[] = {
+	COUNTABLE(PERF_CCU_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_STARVE_CYCLES_FLAG_RETURN, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_BLOCKS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_BLOCKS, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_BLOCK_HIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_BLOCK_HIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_PARTIAL_BLOCK_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_GMEM_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_GMEM_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG0_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG1_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG2_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG3_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG4_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG5_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG6_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_DEPTH_READ_FLAG8_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG0_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG1_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG2_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG3_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG4_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG5_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG6_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_COLOR_READ_FLAG8_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_2D_RD_REQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_CCU_2D_WR_REQ, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter tse_counters[] = {
+	COUNTER(GRAS_PERFCTR_TSE_SEL_0, RBBM_PERFCTR_TSE_0_LO, RBBM_PERFCTR_TSE_0_HI),
+	COUNTER(GRAS_PERFCTR_TSE_SEL_1, RBBM_PERFCTR_TSE_1_LO, RBBM_PERFCTR_TSE_1_HI),
+	COUNTER(GRAS_PERFCTR_TSE_SEL_2, RBBM_PERFCTR_TSE_2_LO, RBBM_PERFCTR_TSE_2_HI),
+	COUNTER(GRAS_PERFCTR_TSE_SEL_3, RBBM_PERFCTR_TSE_3_LO, RBBM_PERFCTR_TSE_3_HI),
+};
+
+static const struct fd_perfcntr_countable tse_countables[] = {
+	COUNTABLE(PERF_TSE_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_CLIPPING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_STALL_CYCLES_RAS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_ZPLANE, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_STARVE_CYCLES_PC, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_INPUT_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_INPUT_NULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_TRIVAL_REJ_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_CLIPPED_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_ZERO_AREA_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_FACENESS_CULLED_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_ZERO_PIXEL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_OUTPUT_NULL_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_OUTPUT_VISIBLE_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_CINVOCATION, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_CPRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_2D_INPUT_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_2D_ALIVE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TSE_CLIP_PLANES, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter ras_counters[] = {
+	COUNTER(GRAS_PERFCTR_RAS_SEL_0, RBBM_PERFCTR_RAS_0_LO, RBBM_PERFCTR_RAS_0_HI),
+	COUNTER(GRAS_PERFCTR_RAS_SEL_1, RBBM_PERFCTR_RAS_1_LO, RBBM_PERFCTR_RAS_1_HI),
+	COUNTER(GRAS_PERFCTR_RAS_SEL_2, RBBM_PERFCTR_RAS_2_LO, RBBM_PERFCTR_RAS_2_HI),
+	COUNTER(GRAS_PERFCTR_RAS_SEL_3, RBBM_PERFCTR_RAS_3_LO, RBBM_PERFCTR_RAS_3_HI),
+};
+
+static const struct fd_perfcntr_countable ras_countables[] = {
+	COUNTABLE(PERF_RAS_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_SUPERTILE_ACTIVE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_STALL_CYCLES_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_STARVE_CYCLES_TSE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_SUPER_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_8X4_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_MASKGEN_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_FULLY_COVERED_SUPER_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_FULLY_COVERED_8X4_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_PRIM_KILLED_INVISILBE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_LRZ_INTF_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RAS_BLOCKS, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter lrz_counters[] = {
+	COUNTER(GRAS_PERFCTR_LRZ_SEL_0, RBBM_PERFCTR_LRZ_0_LO, RBBM_PERFCTR_LRZ_0_HI),
+	COUNTER(GRAS_PERFCTR_LRZ_SEL_1, RBBM_PERFCTR_LRZ_1_LO, RBBM_PERFCTR_LRZ_1_HI),
+	COUNTER(GRAS_PERFCTR_LRZ_SEL_2, RBBM_PERFCTR_LRZ_2_LO, RBBM_PERFCTR_LRZ_2_HI),
+	COUNTER(GRAS_PERFCTR_LRZ_SEL_3, RBBM_PERFCTR_LRZ_3_LO, RBBM_PERFCTR_LRZ_3_HI),
+};
+
+static const struct fd_perfcntr_countable lrz_countables[] = {
+	COUNTABLE(PERF_LRZ_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STARVE_CYCLES_RAS, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_RB, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_VSC, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_VPC, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_LRZ_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_LRZ_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_READ_LATENCY, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_MERGE_CACHE_UPDATING, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_MASKGEN, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_FULL_8X8_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_PARTIAL_8X8_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_TILE_KILLED, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_TOTAL_PIXEL, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_FULLY_COVERED_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_PARTIAL_COVERED_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_FEEDBACK_ACCEPT, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_FEEDBACK_DISCARD, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_FEEDBACK_STALL, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_RB_ZPLANE, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_RB_BPLANE, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_STALL_CYCLES_VC, UINT64, AVERAGE),
+	COUNTABLE(PERF_LRZ_RAS_MASK_TRANS, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter hlsq_counters[] = {
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_0, RBBM_PERFCTR_HLSQ_0_LO, RBBM_PERFCTR_HLSQ_0_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_1, RBBM_PERFCTR_HLSQ_1_LO, RBBM_PERFCTR_HLSQ_1_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_2, RBBM_PERFCTR_HLSQ_2_LO, RBBM_PERFCTR_HLSQ_2_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_3, RBBM_PERFCTR_HLSQ_3_LO, RBBM_PERFCTR_HLSQ_3_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_4, RBBM_PERFCTR_HLSQ_4_LO, RBBM_PERFCTR_HLSQ_4_HI),
+	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_5, RBBM_PERFCTR_HLSQ_5_LO, RBBM_PERFCTR_HLSQ_5_HI),
+// TODO did we loose some HLSQ counters or are they just missing from xml
+//	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_6, RBBM_PERFCTR_HLSQ_6_LO, RBBM_PERFCTR_HLSQ_6_HI),
+//	COUNTER(HLSQ_PERFCTR_HLSQ_SEL_7, RBBM_PERFCTR_HLSQ_7_LO, RBBM_PERFCTR_HLSQ_7_HI),
+};
+
+static const struct fd_perfcntr_countable hlsq_countables[] = {
+	COUNTABLE(PERF_HLSQ_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_STATE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_UCHE_LATENCY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_UCHE_LATENCY_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_FS_STAGE_1X_WAVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_FS_STAGE_2X_WAVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_QUADS, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_CS_INVOCATIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_COMPUTE_DRAWCALLS, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_DUAL_FS_PROG_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_DUAL_VS_PROG_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_FS_BATCH_COUNT_ZERO, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_VS_BATCH_COUNT_ZERO, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_WAVE_PENDING_NO_QUAD, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_STALL_CYCLES_VPC, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_PIXELS, UINT64, AVERAGE),
+	COUNTABLE(PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter pc_counters[] = {
+	COUNTER(PC_PERFCTR_PC_SEL_0, RBBM_PERFCTR_PC_0_LO, RBBM_PERFCTR_PC_0_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_1, RBBM_PERFCTR_PC_1_LO, RBBM_PERFCTR_PC_1_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_2, RBBM_PERFCTR_PC_2_LO, RBBM_PERFCTR_PC_2_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_3, RBBM_PERFCTR_PC_3_LO, RBBM_PERFCTR_PC_3_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_4, RBBM_PERFCTR_PC_4_LO, RBBM_PERFCTR_PC_4_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_5, RBBM_PERFCTR_PC_5_LO, RBBM_PERFCTR_PC_5_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_6, RBBM_PERFCTR_PC_6_LO, RBBM_PERFCTR_PC_6_HI),
+	COUNTER(PC_PERFCTR_PC_SEL_7, RBBM_PERFCTR_PC_7_LO, RBBM_PERFCTR_PC_7_HI),
+};
+
+static const struct fd_perfcntr_countable pc_countables[] = {
+	COUNTABLE(PERF_PC_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_VFD, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_TSE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_VPC, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_TESS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_TSE_ONLY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STALL_CYCLES_VPC_ONLY, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_PASS1_TF_STALL_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_INDEX, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_POSITION, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_STARVE_CYCLES_DI, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_VIS_STREAMS_LOADED, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_INSTANCES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_VPC_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_DEAD_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_LIVE_PRIM, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_VERTEX_HITS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_IA_VERTICES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_IA_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_GS_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_HS_INVOCATIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_DS_INVOCATIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_VS_INVOCATIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_GS_INVOCATIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_DS_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_VPC_POS_DATA_TRANSACTION, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_3D_DRAWCALLS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_2D_DRAWCALLS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TESS_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TESS_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TESS_STALL_CYCLES_PC, UINT64, AVERAGE),
+	COUNTABLE(PERF_TESS_STARVE_CYCLES_PC, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_TSE_TRANSACTION, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_TSE_VERTEX, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_TESS_PC_UV_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_TESS_PC_UV_PATCHES, UINT64, AVERAGE),
+	COUNTABLE(PERF_PC_TESS_FACTOR_TRANS, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter rb_counters[] = {
+	COUNTER(RB_PERFCTR_RB_SEL_0, RBBM_PERFCTR_RB_0_LO, RBBM_PERFCTR_RB_0_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_1, RBBM_PERFCTR_RB_1_LO, RBBM_PERFCTR_RB_1_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_2, RBBM_PERFCTR_RB_2_LO, RBBM_PERFCTR_RB_2_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_3, RBBM_PERFCTR_RB_3_LO, RBBM_PERFCTR_RB_3_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_4, RBBM_PERFCTR_RB_4_LO, RBBM_PERFCTR_RB_4_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_5, RBBM_PERFCTR_RB_5_LO, RBBM_PERFCTR_RB_5_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_6, RBBM_PERFCTR_RB_6_LO, RBBM_PERFCTR_RB_6_HI),
+	COUNTER(RB_PERFCTR_RB_SEL_7, RBBM_PERFCTR_RB_7_LO, RBBM_PERFCTR_RB_7_HI),
+};
+
+static const struct fd_perfcntr_countable rb_countables[] = {
+	COUNTABLE(PERF_RB_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_HLSQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_FIFO0_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_FIFO1_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_FIFO2_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STARVE_CYCLES_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STARVE_CYCLES_LRZ_TILE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STARVE_CYCLES_CCU, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STARVE_CYCLES_Z_PLANE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STARVE_CYCLES_BARY_PLANE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_Z_WORKLOAD, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_HLSQ_ACTIVE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_Z_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_Z_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_C_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_C_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_TOTAL_PASS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_Z_PASS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_Z_FAIL, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_S_FAIL, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_BLENDED_FXP_COMPONENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_BLENDED_FP16_COMPONENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_PS_INVOCATIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_ALIVE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_STALL_CYCLES_A2D, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SRC, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_STARVE_CYCLES_DST, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_VALID_PIXELS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_3D_PIXELS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_BLENDER_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_ZPROC_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_CPROC_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_SAMPLER_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_CCU_COLOR_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_CCU_DEPTH_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_VPC, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_INPUT_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_OUTPUT_RB_DST_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_2D_OUTPUT_RB_SRC_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_BLENDED_FP32_COMPONENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_COLOR_PIX_TILES, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_STALL_CYCLES_CCU, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_EARLY_Z_ARB3_GRANT, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_LATE_Z_ARB3_GRANT, UINT64, AVERAGE),
+	COUNTABLE(PERF_RB_EARLY_Z_SKIP_GRANT, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter rbbm_counters[] = {
+//RESERVED: for kernel
+//	COUNTER(RBBM_PERFCTR_RBBM_SEL_0, RBBM_PERFCTR_RBBM_0_LO, RBBM_PERFCTR_RBBM_0_HI),
+	COUNTER(RBBM_PERFCTR_RBBM_SEL_1, RBBM_PERFCTR_RBBM_1_LO, RBBM_PERFCTR_RBBM_1_HI),
+	COUNTER(RBBM_PERFCTR_RBBM_SEL_2, RBBM_PERFCTR_RBBM_2_LO, RBBM_PERFCTR_RBBM_2_HI),
+	COUNTER(RBBM_PERFCTR_RBBM_SEL_3, RBBM_PERFCTR_RBBM_3_LO, RBBM_PERFCTR_RBBM_3_HI),
+};
+
+static const struct fd_perfcntr_countable rbbm_countables[] = {
+	COUNTABLE(PERF_RBBM_ALWAYS_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_ALWAYS_ON, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_TSE_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_RAS_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_PC_DCALL_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_PC_VSD_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_STATUS_MASKED, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_COM_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_DCOM_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_VBIF_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_VSC_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_TESS_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_UCHE_BUSY, UINT64, AVERAGE),
+	COUNTABLE(PERF_RBBM_HLSQ_BUSY, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter sp_counters[] = {
+//RESERVED: for kernel
+//	COUNTER(SP_PERFCTR_SP_SEL_0,  RBBM_PERFCTR_SP_0_LO,  RBBM_PERFCTR_SP_0_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_1,  RBBM_PERFCTR_SP_1_LO,  RBBM_PERFCTR_SP_1_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_2,  RBBM_PERFCTR_SP_2_LO,  RBBM_PERFCTR_SP_2_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_3,  RBBM_PERFCTR_SP_3_LO,  RBBM_PERFCTR_SP_3_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_4,  RBBM_PERFCTR_SP_4_LO,  RBBM_PERFCTR_SP_4_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_5,  RBBM_PERFCTR_SP_5_LO,  RBBM_PERFCTR_SP_5_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_6,  RBBM_PERFCTR_SP_6_LO,  RBBM_PERFCTR_SP_6_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_7,  RBBM_PERFCTR_SP_7_LO,  RBBM_PERFCTR_SP_7_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_8,  RBBM_PERFCTR_SP_8_LO,  RBBM_PERFCTR_SP_8_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_9,  RBBM_PERFCTR_SP_9_LO,  RBBM_PERFCTR_SP_9_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_10, RBBM_PERFCTR_SP_10_LO, RBBM_PERFCTR_SP_10_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_11, RBBM_PERFCTR_SP_11_LO, RBBM_PERFCTR_SP_11_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_12, RBBM_PERFCTR_SP_12_LO, RBBM_PERFCTR_SP_12_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_13, RBBM_PERFCTR_SP_13_LO, RBBM_PERFCTR_SP_13_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_14, RBBM_PERFCTR_SP_14_LO, RBBM_PERFCTR_SP_14_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_15, RBBM_PERFCTR_SP_15_LO, RBBM_PERFCTR_SP_15_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_16, RBBM_PERFCTR_SP_16_LO, RBBM_PERFCTR_SP_16_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_17, RBBM_PERFCTR_SP_17_LO, RBBM_PERFCTR_SP_17_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_18, RBBM_PERFCTR_SP_18_LO, RBBM_PERFCTR_SP_18_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_19, RBBM_PERFCTR_SP_19_LO, RBBM_PERFCTR_SP_19_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_20, RBBM_PERFCTR_SP_20_LO, RBBM_PERFCTR_SP_20_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_21, RBBM_PERFCTR_SP_21_LO, RBBM_PERFCTR_SP_21_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_22, RBBM_PERFCTR_SP_22_LO, RBBM_PERFCTR_SP_22_HI),
+	COUNTER(SP_PERFCTR_SP_SEL_23, RBBM_PERFCTR_SP_23_LO, RBBM_PERFCTR_SP_23_HI),
+};
+
+static const struct fd_perfcntr_countable sp_countables[] = {
+	COUNTABLE(PERF_SP_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ALU_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_EFU_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_STALL_CYCLES_VPC, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_STALL_CYCLES_TP, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_STALL_CYCLES_RB, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_NON_EXECUTION_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_CONTEXTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_CONTEXT_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_CTRL_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_LOAD_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_EMIT_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_NOP_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_WAIT_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_FETCH_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_IDLE_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_END_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_LONG_SYNC_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_SHORT_SYNC_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WAVE_JOIN_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LM_ATOMICS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GM_ATOMICS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_BARY_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ADDR_LOCK_COUNT, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_UCHE_READ_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_UCHE_WRITE_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_EXPORT_VPC_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_EXPORT_RB_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_PIXELS_KILLED, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ICL1_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ICL1_MISSES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_HS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_DS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_CS_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GPR_READ, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GPR_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LM_BANK_CONFLICTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_TEX_CONTROL_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LOAD_CONTROL_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_FLOW_CONTROL_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LM_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_DISPATCHER_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_SEQUENCER_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_STARVE_CYCLES_HLSQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_NON_EXECUTION_LS_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WORKING_EU, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ANY_EU_WORKING, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WORKING_EU_FS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ANY_EU_WORKING_FS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WORKING_EU_VS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ANY_EU_WORKING_VS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_WORKING_EU_CS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_ANY_EU_WORKING_CS_STAGE, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GPR_READ_PREFETCH, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GPR_READ_CONFLICT, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GPR_WRITE_CONFLICT, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GM_LOAD_LATENCY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_GM_LOAD_LATENCY_SAMPLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_SP_EXECUTABLE_WAVES, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter tp_counters[] = {
+	COUNTER(TPL1_PERFCTR_TP_SEL_0,  RBBM_PERFCTR_TP_0_LO,  RBBM_PERFCTR_TP_0_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_1,  RBBM_PERFCTR_TP_1_LO,  RBBM_PERFCTR_TP_1_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_2,  RBBM_PERFCTR_TP_2_LO,  RBBM_PERFCTR_TP_2_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_3,  RBBM_PERFCTR_TP_3_LO,  RBBM_PERFCTR_TP_3_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_4,  RBBM_PERFCTR_TP_4_LO,  RBBM_PERFCTR_TP_4_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_5,  RBBM_PERFCTR_TP_5_LO,  RBBM_PERFCTR_TP_5_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_6,  RBBM_PERFCTR_TP_6_LO,  RBBM_PERFCTR_TP_6_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_7,  RBBM_PERFCTR_TP_7_LO,  RBBM_PERFCTR_TP_7_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_8,  RBBM_PERFCTR_TP_8_LO,  RBBM_PERFCTR_TP_8_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_9,  RBBM_PERFCTR_TP_9_LO,  RBBM_PERFCTR_TP_9_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_10, RBBM_PERFCTR_TP_10_LO, RBBM_PERFCTR_TP_10_HI),
+	COUNTER(TPL1_PERFCTR_TP_SEL_11, RBBM_PERFCTR_TP_11_LO, RBBM_PERFCTR_TP_11_HI),
+};
+
+static const struct fd_perfcntr_countable tp_countables[] = {
+	COUNTABLE(PERF_TP_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_LATENCY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_LATENCY_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_SAMPLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_LATENCY, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_CACHELINE_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_CACHELINE_MISSES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_SP_TP_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_TP_SP_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_RECEIVED, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_OFFSET, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_SHADOW, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_ARRAY, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_GRADIENT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_1D, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_2D, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_BUFFER, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_3D, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_CUBE, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_DIVERGENT_QUADS_RECEIVED, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_PRT_NON_RESIDENT_EVENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS_MIP, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS_ANISO, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_OUTPUT_PIXELS_ZERO_LOD, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FLAG_CACHE_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FLAG_CACHE_MISSES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_5_L2_REQUESTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_TPA2TPC_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_MISSES_ASTC_1TILE, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_MISSES_ASTC_2TILE, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_MISSES_ASTC_4TILE, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_5_L2_COMPRESS_REQS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_5_L2_COMPRESS_MISS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_BANK_CONFLICT, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_5_MISS_LATENCY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_5_MISS_LATENCY_TRANS, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_QUADS_CONSTANT_MULTIPLIED, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FRONTEND_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_TAG_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_DATA_WRITE_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_PRE_L1_DECOM_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_BACKEND_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_FLAG_CACHE_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_L1_5_CACHE_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_STARVE_CYCLES_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_TP_STARVE_CYCLES_UCHE, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter uche_counters[] = {
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_0,  RBBM_PERFCTR_UCHE_0_LO,  RBBM_PERFCTR_UCHE_0_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_1,  RBBM_PERFCTR_UCHE_1_LO,  RBBM_PERFCTR_UCHE_1_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_2,  RBBM_PERFCTR_UCHE_2_LO,  RBBM_PERFCTR_UCHE_2_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_3,  RBBM_PERFCTR_UCHE_3_LO,  RBBM_PERFCTR_UCHE_3_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_4,  RBBM_PERFCTR_UCHE_4_LO,  RBBM_PERFCTR_UCHE_4_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_5,  RBBM_PERFCTR_UCHE_5_LO,  RBBM_PERFCTR_UCHE_5_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_6,  RBBM_PERFCTR_UCHE_6_LO,  RBBM_PERFCTR_UCHE_6_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_7,  RBBM_PERFCTR_UCHE_7_LO,  RBBM_PERFCTR_UCHE_7_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_8,  RBBM_PERFCTR_UCHE_8_LO,  RBBM_PERFCTR_UCHE_8_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_9,  RBBM_PERFCTR_UCHE_9_LO,  RBBM_PERFCTR_UCHE_9_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_10, RBBM_PERFCTR_UCHE_10_LO, RBBM_PERFCTR_UCHE_10_HI),
+	COUNTER(UCHE_PERFCTR_UCHE_SEL_11, RBBM_PERFCTR_UCHE_11_LO, RBBM_PERFCTR_UCHE_11_HI),
+};
+
+static const struct fd_perfcntr_countable uche_countables[] = {
+	COUNTABLE(PERF_UCHE_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_STALL_CYCLES_ARBITER, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_LATENCY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_LATENCY_SAMPLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_TP, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_VFD, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_HLSQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_READ_REQUESTS_TP, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_READ_REQUESTS_VFD, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_READ_REQUESTS_HLSQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_READ_REQUESTS_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_READ_REQUESTS_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_WRITE_REQUESTS_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_WRITE_REQUESTS_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VPC, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VSC, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_EVICTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ0, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ1, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ2, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ3, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ4, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ5, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ6, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_BANK_REQ7, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH0, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH1, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_GMEM_READ_BEATS, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_TPH_REF_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_TPH_VICTIM_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_TPH_EXT_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_STALL_WRITE_DATA, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_DCMP_LATENCY_SAMPLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_DCMP_LATENCY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_PC, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_READ_REQUESTS_PC, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_RAM_READ_REQ, UINT64, AVERAGE),
+	COUNTABLE(PERF_UCHE_RAM_WRITE_REQ, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter vfd_counters[] = {
+	COUNTER(VFD_PERFCTR_VFD_SEL_0, RBBM_PERFCTR_VFD_0_LO, RBBM_PERFCTR_VFD_0_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_1, RBBM_PERFCTR_VFD_1_LO, RBBM_PERFCTR_VFD_1_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_2, RBBM_PERFCTR_VFD_2_LO, RBBM_PERFCTR_VFD_2_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_3, RBBM_PERFCTR_VFD_3_LO, RBBM_PERFCTR_VFD_3_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_4, RBBM_PERFCTR_VFD_4_LO, RBBM_PERFCTR_VFD_4_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_5, RBBM_PERFCTR_VFD_5_LO, RBBM_PERFCTR_VFD_5_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_6, RBBM_PERFCTR_VFD_6_LO, RBBM_PERFCTR_VFD_6_HI),
+	COUNTER(VFD_PERFCTR_VFD_SEL_7, RBBM_PERFCTR_VFD_7_LO, RBBM_PERFCTR_VFD_7_HI),
+};
+
+static const struct fd_perfcntr_countable vfd_countables[] = {
+	COUNTABLE(PERF_VFD_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_VPC_ALLOC, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_SP_INFO, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STALL_CYCLES_SP_ATTR, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_STARVE_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_RBUFFER_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_ATTR_INFO_FIFO_FULL, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_DECODED_ATTRIBUTE_BYTES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_NUM_ATTRIBUTES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_UPPER_SHADER_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_LOWER_SHADER_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_MODE_0_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_MODE_1_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_MODE_2_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_MODE_3_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_MODE_4_FIBERS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFD_TOTAL_VERTICES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_INDEX, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_PROG, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFDP_STARVE_CYCLES_PC, UINT64, AVERAGE),
+	COUNTABLE(PERF_VFDP_VS_STAGE_WAVES, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter vpc_counters[] = {
+	COUNTER(VPC_PERFCTR_VPC_SEL_0, RBBM_PERFCTR_VPC_0_LO, RBBM_PERFCTR_VPC_0_HI),
+	COUNTER(VPC_PERFCTR_VPC_SEL_1, RBBM_PERFCTR_VPC_1_LO, RBBM_PERFCTR_VPC_1_HI),
+	COUNTER(VPC_PERFCTR_VPC_SEL_2, RBBM_PERFCTR_VPC_2_LO, RBBM_PERFCTR_VPC_2_HI),
+	COUNTER(VPC_PERFCTR_VPC_SEL_3, RBBM_PERFCTR_VPC_3_LO, RBBM_PERFCTR_VPC_3_HI),
+	COUNTER(VPC_PERFCTR_VPC_SEL_4, RBBM_PERFCTR_VPC_4_LO, RBBM_PERFCTR_VPC_4_HI),
+	COUNTER(VPC_PERFCTR_VPC_SEL_5, RBBM_PERFCTR_VPC_5_LO, RBBM_PERFCTR_VPC_5_HI),
+};
+
+static const struct fd_perfcntr_countable vpc_countables[] = {
+	COUNTABLE(PERF_VPC_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STALL_CYCLES_VFD_WACK, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STALL_CYCLES_PC, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STALL_CYCLES_SP_LM, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STARVE_CYCLES_SP, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STARVE_CYCLES_LRZ, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_PC_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_SP_COMPONENTS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STALL_CYCLES_VPCRAM_POS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_LRZ_ASSIGN_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_RB_VISIBLE_PRIMITIVES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_LM_TRANSACTION, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STREAMOUT_TRANSACTION, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_VS_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_PS_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_VS_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_PS_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_STARVE_CYCLES_RB, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_NUM_VPCRAM_READ_POS, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_WIT_FULL_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_VPCRAM_FULL_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_LM_FULL_WAIT_FOR_INTP_END, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_NUM_VPCRAM_WRITE, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_NUM_VPCRAM_READ_SO, UINT64, AVERAGE),
+	COUNTABLE(PERF_VPC_NUM_ATTR_REQ_LM, UINT64, AVERAGE),
+};
+
+static const struct fd_perfcntr_counter vsc_counters[] = {
+	COUNTER(VSC_PERFCTR_VSC_SEL_0, RBBM_PERFCTR_VSC_0_LO, RBBM_PERFCTR_VSC_0_HI),
+	COUNTER(VSC_PERFCTR_VSC_SEL_1, RBBM_PERFCTR_VSC_1_LO, RBBM_PERFCTR_VSC_1_HI),
+};
+
+static const struct fd_perfcntr_countable vsc_countables[] = {
+	COUNTABLE(PERF_VSC_BUSY_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VSC_WORKING_CYCLES, UINT64, AVERAGE),
+	COUNTABLE(PERF_VSC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
+	COUNTABLE(PERF_VSC_EOT_NUM, UINT64, AVERAGE),
+	COUNTABLE(PERF_VSC_INPUT_TILES, UINT64, AVERAGE),
+};
+
+const struct fd_perfcntr_group a6xx_perfcntr_groups[] = {
+	GROUP("CP", cp_counters, cp_countables),
+	GROUP("CCU", ccu_counters, ccu_countables),
+	GROUP("TSE", tse_counters, tse_countables),
+	GROUP("RAS", ras_counters, ras_countables),
+	GROUP("LRZ", lrz_counters, lrz_countables),
+	GROUP("HLSQ", hlsq_counters, hlsq_countables),
+	GROUP("PC", pc_counters, pc_countables),
+	GROUP("RB", rb_counters, rb_countables),
+	GROUP("RBBM", rbbm_counters, rbbm_countables),
+	GROUP("SP", sp_counters, sp_countables),
+	GROUP("TP", tp_counters, tp_countables),
+	GROUP("UCHE", uche_counters, uche_countables),
+	GROUP("VFD", vfd_counters, vfd_countables),
+	GROUP("VPC", vpc_counters, vpc_countables),
+	GROUP("VSC", vsc_counters, vsc_countables),
+//	GROUP("VBIF", vbif_counters, vbif_countables),
+};
+
+const unsigned a6xx_num_perfcntr_groups = ARRAY_SIZE(a6xx_perfcntr_groups);
+
+#endif /* FD5_PERFCNTR_H_ */
diff --git a/src/freedreno/perfcntrs/freedreno_perfcntr.h b/src/freedreno/perfcntrs/freedreno_perfcntr.h
new file mode 100644
index 00000000000..6d61f673327
--- /dev/null
+++ b/src/freedreno/perfcntrs/freedreno_perfcntr.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2018 Rob Clark <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <[email protected]>
+ */
+
+#ifndef FREEDRENO_PERFCNTR_H_
+#define FREEDRENO_PERFCNTR_H_
+
+/*
+ * Mapping very closely to the AMD_performance_monitor extension, adreno has
+ * groups of performance counters where each group has N counters, which can
+ * select from M different countables (things that can be counted), where
+ * generally M > N.
+ */
+
+/* Describes a single counter: */
+struct fd_perfcntr_counter {
+	/* offset of the select register to choose what to count: */
+	unsigned select_reg;
+	/* offset of the lo/hi 32b to read current counter value: */
+	unsigned counter_reg_lo;
+	unsigned counter_reg_hi;
+	/* Optional, most counters don't have enable/clear registers: */
+	unsigned enable;
+	unsigned clear;
+};
+
+
+enum fd_perfcntr_type {
+	FD_PERFCNTR_TYPE_UINT64,
+	FD_PERFCNTR_TYPE_UINT,
+	FD_PERFCNTR_TYPE_FLOAT,
+	FD_PERFCNTR_TYPE_PERCENTAGE,
+	FD_PERFCNTR_TYPE_BYTES,
+	FD_PERFCNTR_TYPE_MICROSECONDS,
+	FD_PERFCNTR_TYPE_HZ,
+	FD_PERFCNTR_TYPE_DBM,
+	FD_PERFCNTR_TYPE_TEMPERATURE,
+	FD_PERFCNTR_TYPE_VOLTS,
+	FD_PERFCNTR_TYPE_AMPS,
+	FD_PERFCNTR_TYPE_WATTS,
+};
+
+/* Whether an average value per frame or a cumulative value should be
+ * displayed.
+ */
+enum fd_perfcntr_result_type {
+	FD_PERFCNTR_RESULT_TYPE_AVERAGE,
+	FD_PERFCNTR_RESULT_TYPE_CUMULATIVE,
+};
+
+
+/* Describes a single countable: */
+struct fd_perfcntr_countable {
+	const char *name;
+	/* selector register enum value to select this countable: */
+	unsigned selector;
+
+	/* description of the countable: */
+	enum fd_perfcntr_type query_type;
+	enum fd_perfcntr_result_type result_type;
+};
+
+/* Describes an entire counter group: */
+struct fd_perfcntr_group {
+	const char *name;
+	unsigned num_counters;
+	const struct fd_perfcntr_counter *counters;
+	unsigned num_countables;
+	const struct fd_perfcntr_countable *countables;
+};
+
+#define COUNTER(_sel, _lo, _hi) {  \
+	.select_reg = REG(_sel),       \
+	.counter_reg_lo = REG(_lo),    \
+	.counter_reg_hi = REG(_hi),    \
+}
+
+#define COUNTER2(_sel, _lo, _hi, _en, _clr) { \
+	.select_reg     = REG(_sel),  \
+	.counter_reg_lo = REG(_lo),   \
+	.counter_reg_hi = REG(_hi),   \
+	.enable         = REG(_en),   \
+	.clear          = REG(_clr),  \
+}
+
+#define COUNTABLE(_selector, _query_type, _result_type) {            \
+	.name        = #_selector,                                       \
+	.selector    = _selector,                                        \
+	.query_type  = FD_PERFCNTR_TYPE_ ## _query_type,                 \
+	.result_type = FD_PERFCNTR_RESULT_TYPE_ ## _result_type,         \
+}
+
+#define GROUP(_name, _counters, _countables) {   \
+	.name           = _name,                     \
+	.num_counters   = ARRAY_SIZE(_counters),     \
+	.counters       = _counters,                 \
+	.num_countables = ARRAY_SIZE(_countables),   \
+	.countables     = _countables,               \
+}
+
+#endif /* FREEDRENO_PERFCNTR_H_ */
diff --git a/src/freedreno/perfcntrs/meson.build b/src/freedreno/perfcntrs/meson.build
new file mode 100644
index 00000000000..8e110633c3e
--- /dev/null
+++ b/src/freedreno/perfcntrs/meson.build
@@ -0,0 +1,37 @@
+# Copyright © 2018 Rob Clark
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+libfreedreno_perfcntrs_files = files(
+  'fd2_perfcntr.c',
+  'fd5_perfcntr.c',
+  'fd6_perfcntr.c',
+  'freedreno_perfcntr.h',
+)
+
+libfreedreno_perfcntrs = static_library(
+  'freedreno_perfcntrs',
+  [libfreedreno_perfcntrs_files, freedreno_xml_header_files],
+  include_directories : [inc_freedreno, inc_common],
+  c_args : [c_vis_args, no_override_init_args],
+  cpp_args : [cpp_vis_args],
+  dependencies : idep_nir_headers,
+  build_by_default : false,
+)
+