diff options
| author | Rob Clark <[email protected]> | 2019-08-01 14:22:46 -0700 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2019-08-13 08:11:26 -0700 |
| commit | 4a188e421522f10af85e5bb8c42c60666d02e778 (patch) | |
| tree | 0d05ba7747fb7b4a06f9ef136d62395fe069eb8e /src/freedreno/ir3/ir3_nir.c | |
| parent | 7f1e3391c6d2baae60dd797cd05aaff730ab5110 (diff) | |
freedreno/ir3: track # of driver params
To avoid emitting unneeded const state.
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/freedreno/ir3/ir3_nir.c')
| -rw-r--r-- | src/freedreno/ir3/ir3_nir.c | 41 |
1 files changed, 31 insertions, 10 deletions
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index 260702ba3c7..f258c46f94b 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -335,6 +335,24 @@ ir3_nir_scan_driver_consts(nir_shader *shader, } else { layout->num_ubos = shader->info.num_ubos; } + break; + case nir_intrinsic_load_base_vertex: + case nir_intrinsic_load_first_vertex: + layout->num_driver_params = + MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1); + break; + case nir_intrinsic_load_user_clip_plane: + layout->num_driver_params = + MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1); + break; + case nir_intrinsic_load_num_work_groups: + layout->num_driver_params = + MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1); + break; + case nir_intrinsic_load_local_group_size: + layout->num_driver_params = + MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1); + break; default: break; } @@ -353,8 +371,17 @@ ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir) ir3_nir_scan_driver_consts(nir, const_state); + if ((compiler->gpu_id < 500) && + (shader->stream_output.num_outputs > 0)) { + const_state->num_driver_params = + MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1); + } + + /* num_driver_params is scalar, align to vec4: */ + const_state->num_driver_params = align(const_state->num_driver_params, 4); + debug_assert((shader->ubo_state.size % 16) == 0); - unsigned constoff = align(shader->ubo_state.size / 16, 4); + unsigned constoff = align(shader->ubo_state.size / 16, 8); unsigned ptrsz = ir3_pointer_size(compiler); if (const_state->num_ubos > 0) { @@ -374,15 +401,9 @@ ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir) constoff += align(cnt, 4) / 4; } - unsigned num_driver_params = 0; - if (shader->type == MESA_SHADER_VERTEX) { - num_driver_params = IR3_DP_VS_COUNT; - } else if (shader->type == MESA_SHADER_COMPUTE) { - num_driver_params = IR3_DP_CS_COUNT; - } - - const_state->offsets.driver_param = constoff; - constoff += align(num_driver_params, 4) / 4; + if (const_state->num_driver_params > 0) + const_state->offsets.driver_param = constoff; + constoff += const_state->num_driver_params / 4; if ((shader->type == MESA_SHADER_VERTEX) && (compiler->gpu_id < 500) && |