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| author | Kristian H. Kristensen <[email protected]> | 2020-05-13 13:19:57 -0700 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2020-05-13 20:24:33 -0700 |
| commit | 14969aab11effa1500f114314c9b8879821b8b24 (patch) | |
| tree | f1bba9a2eaf6c1eb8e04ea0fc3a9a0013679ea89 /src/compiler/nir/nir_intrinsics.py | |
| parent | 4627bfcd69544780e30c069b77967cfb92c9d7e0 (diff) | |
freedreno/ir3: Drop wrmask for ir3 local and global store intrinsics
These intrinsics are supposed to map to the underlying hardware
instructions, which don't have wrmask. We use them when we lower
store_output in the geometry pipeline and since store_output gets
lowered to temps, we always see full wrmasks there.
Diffstat (limited to 'src/compiler/nir/nir_intrinsics.py')
| -rw-r--r-- | src/compiler/nir/nir_intrinsics.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 611955ffa02..00098203d2e 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -836,7 +836,7 @@ intrinsic("end_patch_ir3") # between geometry stages - perhaps it's explicit access to the vertex cache. # src[] = { value, offset }. -store("shared_ir3", 2, [BASE, WRMASK, ALIGN_MUL, ALIGN_OFFSET]) +store("shared_ir3", 2, [BASE, ALIGN_MUL, ALIGN_OFFSET]) # src[] = { offset }. load("shared_ir3", 1, [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) @@ -846,7 +846,7 @@ load("shared_ir3", 1, [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) # src[] = { value, address(vec2 of hi+lo uint32_t), offset }. # const_index[] = { write_mask, align_mul, align_offset } -intrinsic("store_global_ir3", [0, 2, 1], indices=[WRMASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) +intrinsic("store_global_ir3", [0, 2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET]) # src[] = { address(vec2 of hi+lo uint32_t), offset }. # const_index[] = { access, align_mul, align_offset } intrinsic("load_global_ir3", [2, 1], dest_comp=0, indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) |