nir: Rename Boolean-related opcodes to include 32 in the name

This is a squash of a bunch of individual changes:

    nir/builder: Generate 32-bit bool opcodes transparently

    nir/algebraic: Remap Boolean opcodes to the 32-bit variant

    Use 32-bit opcodes in the NIR producers and optimizations

        Generated with a little hand-editing and the following sed commands:

        sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
        sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
        sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
        sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c
        sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c
        sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c

     Use 32-bit opcodes in the NIR back-ends

        Generated with a little hand-editing and the following sed commands:

        sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
        sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
        sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
        sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c
        sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c
        sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c

Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Tested-by: Bas Nieuwenhuizen <[email protected]>

1 files changed, 38 insertions, 1 deletions

diff --git a/src/compiler/nir/nir_builder_opcodes_h.py b/src/compiler/nir/nir_builder_opcodes_h.py
index 34b8c4371e1..5c38818d4ec 100644
--- a/src/compiler/nir/nir_builder_opcodes_h.py
+++ b/src/compiler/nir/nir_builder_opcodes_h.py
@@ -27,6 +27,36 @@ template = """\
 #define _NIR_BUILDER_OPCODES_
 
 <%
+opcode_remap = {
+   'flt' : 'flt32',
+   'fge' : 'fge32',
+   'feq' : 'feq32',
+   'fne' : 'fne32',
+   'ilt' : 'ilt32',
+   'ige' : 'ige32',
+   'ieq' : 'ieq32',
+   'ine' : 'ine32',
+   'ult' : 'ult32',
+   'uge' : 'uge32',
+
+   'ball_iequal2' : 'b32all_iequal2',
+   'ball_iequal3' : 'b32all_iequal3',
+   'ball_iequal4' : 'b32all_iequal4',
+   'bany_inequal2' : 'b32any_inequal2',
+   'bany_inequal3' : 'b32any_inequal3',
+   'bany_inequal4' : 'b32any_inequal4',
+   'ball_fequal2' : 'b32all_fequal2',
+   'ball_fequal3' : 'b32all_fequal3',
+   'ball_fequal4' : 'b32all_fequal4',
+   'bany_fnequal2' : 'b32any_fnequal2',
+   'bany_fnequal3' : 'b32any_fnequal3',
+   'bany_fnequal4' : 'b32any_fnequal4',
+
+   'bcsel' : 'b32csel',
+}
+
+opcode_remap32 = { op32 : op for op, op32 in opcode_remap.items() }
+
 def src_decl_list(num_srcs):
    return ', '.join('nir_ssa_def *src' + str(i) for i in range(num_srcs))
 
@@ -35,8 +65,15 @@ def src_list(num_srcs):
 %>
 
 % for name, opcode in sorted(opcodes.items()):
+  % if name in opcode_remap:
+    <% continue %>
+  % elif name in opcode_remap32:
+    <% builder_name = opcode_remap32[name] %>
+  % else:
+    <% builder_name = name %>
+  % endif
 static inline nir_ssa_def *
-nir_${name}(nir_builder *build, ${src_decl_list(opcode.num_inputs)})
+nir_${builder_name}(nir_builder *build, ${src_decl_list(opcode.num_inputs)})
 {
    return nir_build_alu(build, nir_op_${name}, ${src_list(opcode.num_inputs)});
 }