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authorMarek Olšák <[email protected]>2018-11-09 16:51:47 -0500
committerMarek Olšák <[email protected]>2019-04-04 09:53:24 -0400
commitfe3bfd7971bf20a663e949a0a5633492a9412889 (patch)
tree5572229f138fdc3be5bc987eebf773260fd582a1 /src/amd
parente457454cb6279ffaeb4c913fa812249e7e81e1e8 (diff)
radeonsi/gfx9: add support for PIPE_ALIGNED=0
Needed by displayable DCC. We need to flush L2 after rendering if PIPE_ALIGNED=0 and DCC is enabled.
Diffstat (limited to 'src/amd')
0 files changed, 0 insertions, 0 deletions