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authorSamuel Pitoiset <[email protected]>2018-05-16 16:02:04 +0200
committerSamuel Pitoiset <[email protected]>2018-05-22 15:53:15 +0200
commitd8a61d32322b2a12bb431d217c5798d8234d6c13 (patch)
tree7632093eded5f0dcb5543917b5798c096fa06321 /src/amd
parentfe2649d3ad7dbf47000f2e1403c3c279d09f7dc0 (diff)
radv: set amdgpu-32bit-address-high-bits LLVM attribute
Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/vulkan/radv_nir_to_llvm.c6
-rw-r--r--src/amd/vulkan/radv_shader.c1
-rw-r--r--src/amd/vulkan/radv_shader.h1
3 files changed, 8 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 2d91ded7fe5..3f32f62cdc4 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -511,6 +511,12 @@ create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
}
}
+ if (options->address32_hi) {
+ ac_llvm_add_target_dep_function_attr(main_function,
+ "amdgpu-32bit-address-high-bits",
+ options->address32_hi);
+ }
+
if (max_workgroup_size) {
ac_llvm_add_target_dep_function_attr(main_function,
"amdgpu-max-work-group-size",
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 7589d9c88a5..6ccbe81effa 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -482,6 +482,7 @@ shader_variant_create(struct radv_device *device,
device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
options->record_llvm_ir = device->keep_shader_info;
options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
+ options->address32_hi = device->physical_device->rad_info.address32_hi;
if (options->supports_spill)
tm_options |= AC_TM_SUPPORTS_SPILL;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 679fa442798..05de188e3f3 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -123,6 +123,7 @@ struct radv_nir_compiler_options {
enum radeon_family family;
enum chip_class chip_class;
uint32_t tess_offchip_block_dw_size;
+ uint32_t address32_hi;
};
enum radv_ud_index {