diff options
| author | Samuel Pitoiset <[email protected]> | 2018-07-09 11:33:28 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-07-18 13:44:06 +0200 |
| commit | 946cf3f39fce79c692f7eab98196278c3f5ae478 (patch) | |
| tree | 316a2afb1797acfaa10bad1bd96e3b5e85abb8c8 /src/amd | |
| parent | 4d99caf590a40c41d07bb13a0b5c4c87edcc5216 (diff) | |
radv: add support for non-inverted conditional rendering
By default, our internal rendering commands are discarded
only if the predicate is non-zero (ie. DRAW_VISIBLE). But
VK_EXT_conditional_rendering also allows to discard commands
when the predicate is zero, which means we have to use a
different flag.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_meta_fast_clear.c | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 3 | ||||
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 17 |
3 files changed, 17 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index 136557080d9..d3cd445d97f 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -571,7 +571,7 @@ radv_emit_set_predication_state_from_image(struct radv_cmd_buffer *cmd_buffer, va += image->dcc_pred_offset; } - si_emit_set_predication_state(cmd_buffer, va); + si_emit_set_predication_state(cmd_buffer, true, va); } /** diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 338cb07b3e1..c697964273d 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1088,7 +1088,8 @@ void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum radv_cmd_flush_bits flush_bits, uint64_t gfx9_eop_bug_va); void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer); -void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va); +void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, + bool inverted, uint64_t va); void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint64_t dest_va, uint64_t size); diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index e3c1e2ff7e7..5b88fdcf3ed 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -1002,12 +1002,23 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) /* sets the CP predication state using a boolean stored at va */ void -si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va) +si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, + bool inverted, uint64_t va) { uint32_t op = 0; - if (va) - op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE; + if (va) { + op = PRED_OP(PREDICATION_OP_BOOL64); + + /* By default, our internal rendering commands are discarded + * only if the predicate is non-zero (ie. DRAW_VISIBLE). But + * VK_EXT_conditional_rendering also allows to discard commands + * when the predicate is zero, which means we have to use a + * different flag. + */ + op |= inverted ? PREDICATION_DRAW_VISIBLE : + PREDICATION_DRAW_NOT_VISIBLE; + } if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0)); radeon_emit(cmd_buffer->cs, op); |