diff options
| author | Samuel Pitoiset <[email protected]> | 2019-07-02 14:50:28 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-07-03 08:52:01 +0200 |
| commit | a7b6a869a78724c55a6699969fe1d776713ae7ec (patch) | |
| tree | ae09317ad430cbf8dc8176675330c5f42451e1ba /src/amd | |
| parent | 6baa453dd53679c6e1458adcdd7ee44c7b9f3506 (diff) | |
radv: only allocate a 32-bit value for the TC-compat range metadata
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index eeccce0d82f..dc598d9eecf 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -990,8 +990,8 @@ radv_image_alloc_htile(struct radv_image *image) * have to be fixed by updating ZRANGE_PRECISION when doing * fast depth clears to 0.0f. */ - image->tc_compat_zrange_offset = image->clear_value_offset + 8; - image->size = image->clear_value_offset + 16; + image->tc_compat_zrange_offset = image->size; + image->size = image->tc_compat_zrange_offset + 4; } image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment); } |