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authorBas Nieuwenhuizen <[email protected]>2018-05-12 23:50:04 +0200
committerBas Nieuwenhuizen <[email protected]>2018-05-14 18:58:20 +0200
commit3d4d388e3929d7948b62d90867357aecbfba5aeb (patch)
treef39c61ddf84d3519f7684761102a894421d834d1 /src/amd/vulkan/radv_private.h
parente361970ed73d0f0a11d93a718dbfe2bf4f38b56d (diff)
radv: Fix up 2_10_10_10 alpha sign.
Pre-Vega HW always interprets the alpha for this format as unsigned, so we have to implement a fixup to do the sign correctly for signed formats. v2: Improve indexing mess. CC: 18.0 18.1 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480 Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_private.h')
-rw-r--r--src/amd/vulkan/radv_private.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 4805acab280..e3eed887fae 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -352,6 +352,7 @@ struct radv_pipeline_cache {
struct radv_pipeline_key {
uint32_t instance_rate_inputs;
uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+ uint64_t vertex_alpha_adjust;
unsigned tess_input_vertices;
uint32_t col_format;
uint32_t is_int8;