diff options
| author | Samuel Pitoiset <[email protected]> | 2018-06-19 14:25:48 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-06-20 13:21:42 +0200 |
| commit | 70c1bee1872f3a38c6db7e79c6ec56056f1c8f7c (patch) | |
| tree | 904eacac42ae74f69854844d5feff5c7ca6e63ae /src/amd/vulkan/radv_pipeline.c | |
| parent | 20170865db0d8d78f217ea1eaf49eff4a4c0bfc1 (diff) | |
radv: do not use an user SGPR for the sample position offset
We know the number of samples at compile time.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 54faddf5882..1f01d2ff4d6 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2710,35 +2710,6 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *cs, radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa); radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); - - if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) { - uint32_t offset; - struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET); - uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT]; - if (loc->sgpr_idx == -1) - return; - assert(loc->num_sgprs == 1); - assert(!loc->indirect); - switch (pipeline->graphics.ms.num_samples) { - default: - offset = 0; - break; - case 2: - offset = 1; - break; - case 4: - offset = 3; - break; - case 8: - offset = 7; - break; - case 16: - offset = 15; - break; - } - - radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset); - } } static void |