diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2018-05-12 23:50:04 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2018-05-14 18:58:20 +0200 |
| commit | 3d4d388e3929d7948b62d90867357aecbfba5aeb (patch) | |
| tree | f39c61ddf84d3519f7684761102a894421d834d1 /src/amd/vulkan/radv_pipeline.c | |
| parent | e361970ed73d0f0a11d93a718dbfe2bf4f38b56d (diff) | |
radv: Fix up 2_10_10_10 alpha sign.
Pre-Vega HW always interprets the alpha for this format as unsigned,
so we have to implement a fixup to do the sign correctly for signed
formats.
v2: Improve indexing mess.
CC: 18.0 18.1 <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 7a577dae413..52734a308a9 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1813,13 +1813,36 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline, } for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) { - unsigned binding; - binding = input_state->pVertexAttributeDescriptions[i].binding; + unsigned location = input_state->pVertexAttributeDescriptions[i].location; + unsigned binding = input_state->pVertexAttributeDescriptions[i].binding; if (binding_input_rate & (1u << binding)) { - unsigned location = input_state->pVertexAttributeDescriptions[i].location; key.instance_rate_inputs |= 1u << location; key.instance_rate_divisors[location] = instance_rate_divisors[binding]; } + + if (pipeline->device->physical_device->rad_info.chip_class <= VI && + pipeline->device->physical_device->rad_info.family != CHIP_STONEY) { + VkFormat format = input_state->pVertexAttributeDescriptions[i].format; + uint64_t adjust; + switch(format) { + case VK_FORMAT_A2R10G10B10_SNORM_PACK32: + case VK_FORMAT_A2B10G10R10_SNORM_PACK32: + adjust = RADV_ALPHA_ADJUST_SNORM; + break; + case VK_FORMAT_A2R10G10B10_SSCALED_PACK32: + case VK_FORMAT_A2B10G10R10_SSCALED_PACK32: + adjust = RADV_ALPHA_ADJUST_SSCALED; + break; + case VK_FORMAT_A2R10G10B10_SINT_PACK32: + case VK_FORMAT_A2B10G10R10_SINT_PACK32: + adjust = RADV_ALPHA_ADJUST_SINT; + break; + default: + adjust = 0; + break; + } + key.vertex_alpha_adjust |= adjust << (2 * location); + } } if (pCreateInfo->pTessellationState) @@ -1848,6 +1871,7 @@ radv_fill_shader_keys(struct radv_shader_variant_key *keys, nir_shader **nir) { keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs; + keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust; for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i]; |