diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2018-01-14 02:46:49 +0100 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2018-01-30 22:00:55 +0100 |
| commit | e2bf18030d9793dd9586315763d1cf444d0462a3 (patch) | |
| tree | 7f346a38595a1b7a0b4b9eea0d959075b20acfe7 /src/amd/vulkan/radv_pipeline.c | |
| parent | c80747b32c723cd8032e864a579baa36c8ca80cd (diff) | |
radv: Merge vtx_reuse_depth computation with PM4 generation.
Reviewed-by: Dave Airlie <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 32c381bc49a..3862625e198 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2860,8 +2860,13 @@ radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs, if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10) return; + unsigned vtx_reuse_depth = 30; + if (radv_pipeline_has_tess(pipeline) && + radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) { + vtx_reuse_depth = 14; + } radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, - pipeline->graphics.vtx_reuse_depth); + S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth)); } static void @@ -3178,12 +3183,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline, pipeline->graphics.vtx_emit_num = 2; } - pipeline->graphics.vtx_reuse_depth = 30; - if (radv_pipeline_has_tess(pipeline) && - radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) { - pipeline->graphics.vtx_reuse_depth = 14; - } - if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) { radv_dump_pipeline_stats(device, pipeline); } |