diff options
| author | Samuel Pitoiset <[email protected]> | 2019-06-18 10:30:43 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-06-18 11:24:36 +0200 |
| commit | 864ddda8a3c392a354aecc6653ade54c34333133 (patch) | |
| tree | 25dd09ff3713b37785e853cf831e0b1ae8035f7a /src/amd/vulkan/radv_meta_fast_clear.c | |
| parent | 79a30543eea529c22492067ff57bce8bb88ab83e (diff) | |
radv: check if DCC is enabled per mip not for the whole image
In other words, make use of radv_dcc_enabled() instead of
radv_image_has_dcc() all over the places.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_meta_fast_clear.c')
| -rw-r--r-- | src/amd/vulkan/radv_meta_fast_clear.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index feeb0a1b7ed..6e5fee552b0 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -704,7 +704,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer, assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL); - if (decompress_dcc && radv_image_has_dcc(image)) { + if (decompress_dcc && radv_dcc_enabled(image, subresourceRange->baseMipLevel)) { pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.dcc_decompress_pipeline; } else if (radv_image_has_fmask(image)) { pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.fmask_decompress_pipeline; @@ -712,7 +712,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer, pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline; } - if (radv_image_has_dcc(image)) { + if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) { uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset : image->fce_pred_offset; pred_offset += 8 * subresourceRange->baseMipLevel; @@ -725,7 +725,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer, radv_process_color_image(cmd_buffer, image, subresourceRange, pipeline); - if (radv_image_has_dcc(image)) { + if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) { uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset : image->fce_pred_offset; pred_offset += 8 * subresourceRange->baseMipLevel; @@ -742,7 +742,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer, } } - if (radv_image_has_dcc(image)) { + if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) { /* Clear the image's fast-clear eliminate predicate because * FMASK and DCC also imply a fast-clear eliminate. */ |